Why all this speculation when I'm sure you already know Skylake-X (rename of skylake-e) is getting its own socket, lga-2066 with KabyLake-X and the X299 chipset.
why is the socket so large on the HEDT platform. I mean the only real difference between these sockets, and the ones in consumer desktop is a little more die area dedicated to the memory controller, but the missing graphics should make up for that you would think.
256GB per module? Jesus! Intel better stop dragging its ass on 3D XPoint and get that ball rolling otherwise I'm not sure there's much "point" at all in releasing a product that can't compete with DRAM in either performance or density. Or IBM could be out with it's own phase change memory before Intel gets to pop that cherry.
When? By 2050 DRAM will have had plenty of time to catch up. Intel has already had to delay Optane once, at least publicly, and the fact that they've gone completely silent about the technology suggests to me that they may have run into some serious road blocks. I'm starting to think Intel was telling the truth when they said that 3D XPoint was not PCM memory. So far it seems to be constructed entirely of press releases.
There were some good indications ( http://wccftech.com/intel-skylake-e-lga-3647-hexa-...http://wccftech.com/massive-intel-xeon-e5-xeon-e7-... ) that Skylake-EP will support 6-channel memory, so this is rather odd that MS tries to pretend that nobody knows it and says "up to 32 dimms" instead of "up to 36 dimms" (6 channels, 3 DPC for each of 2 packages). 4 DPC is very unlikely, i'm not really sure it can be ever feasible without additional buffers.
I wonder if any of the DIMM slots were to be dedicated for 3D Xpoint DIMMs only. For example, each socket would have twelve DDR4 + four 3D Xpoint DIMM slots. Double up the socket count to get 32 DIMMs total. This could be handled in two different ways: the extra 3D Point slots as an extra slot across four memory channels (two 2 DPC + four 3 DPC) or simply dedicated memory channels to 3D Xpoint (four 2 DPC DDR4 + two 4 DPC 3D Xpoint). Either way that'd produce 32 DIMMs on a dual socket system without the need for a memory buffer.
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GhostOfAnand - Tuesday, November 1, 2016 - link
Another attempt and Embrace, Extend, and Extinguish.Microsoft, about as innovative as my comment.
GhostOfAnand - Tuesday, November 1, 2016 - link
Good sleuthing, though, Ian.drjlaw - Tuesday, November 1, 2016 - link
Please, explain the Extend and Extinguish steps here. All I see is baseless anti-Microsoft whinging.mlkmade - Tuesday, November 1, 2016 - link
Why all this speculation when I'm sure you already know Skylake-X (rename of skylake-e) is getting its own socket, lga-2066 with KabyLake-X and the X299 chipset.So yes, HEDT and the EP lines are being split.
Unless you really dont know?
Morawka - Tuesday, November 1, 2016 - link
why is the socket so large on the HEDT platform. I mean the only real difference between these sockets, and the ones in consumer desktop is a little more die area dedicated to the memory controller, but the missing graphics should make up for that you would think.ats - Tuesday, November 1, 2016 - link
additional memory channels according to leaks and speculation. sockets aren't dependent on die area but instead based on the number of pins required.mlkmade - Wednesday, November 2, 2016 - link
you know there is more cores and cache right?TheinsanegamerN - Tuesday, November 1, 2016 - link
MCDRAM? Does it come with a side of fries, and can I supersize it?dakishimesan - Wednesday, November 2, 2016 - link
solid joke, i chuckled.Magichands8 - Tuesday, November 1, 2016 - link
256GB per module? Jesus! Intel better stop dragging its ass on 3D XPoint and get that ball rolling otherwise I'm not sure there's much "point" at all in releasing a product that can't compete with DRAM in either performance or density. Or IBM could be out with it's own phase change memory before Intel gets to pop that cherry.Kevin G - Wednesday, November 2, 2016 - link
Intel indicated plans for 1 TB 3D Xpoint DIMMs so there is still a capacity advantage there.Magichands8 - Wednesday, November 2, 2016 - link
When? By 2050 DRAM will have had plenty of time to catch up. Intel has already had to delay Optane once, at least publicly, and the fact that they've gone completely silent about the technology suggests to me that they may have run into some serious road blocks. I'm starting to think Intel was telling the truth when they said that 3D XPoint was not PCM memory. So far it seems to be constructed entirely of press releases.eSyr - Tuesday, November 1, 2016 - link
There were some good indications ( http://wccftech.com/intel-skylake-e-lga-3647-hexa-... http://wccftech.com/massive-intel-xeon-e5-xeon-e7-... ) that Skylake-EP will support 6-channel memory, so this is rather odd that MS tries to pretend that nobody knows it and says "up to 32 dimms" instead of "up to 36 dimms" (6 channels, 3 DPC for each of 2 packages). 4 DPC is very unlikely, i'm not really sure it can be ever feasible without additional buffers.edzieba - Wednesday, November 2, 2016 - link
Holy guacamole, Oculink actually turning up in something!Kevin G - Thursday, November 3, 2016 - link
I wonder if any of the DIMM slots were to be dedicated for 3D Xpoint DIMMs only. For example, each socket would have twelve DDR4 + four 3D Xpoint DIMM slots. Double up the socket count to get 32 DIMMs total. This could be handled in two different ways: the extra 3D Point slots as an extra slot across four memory channels (two 2 DPC + four 3 DPC) or simply dedicated memory channels to 3D Xpoint (four 2 DPC DDR4 + two 4 DPC 3D Xpoint). Either way that'd produce 32 DIMMs on a dual socket system without the need for a memory buffer.