TSMC this week announced a new fabrication process that is tailored specifically for high-performance computing (HPC) products. N4X promises to combine transistor density and design rules of TSMC's N5-family nodes with the ability to drive chips at extra high voltages for higher frequencies, which will be particularly useful for server CPUs and SoCs. Interestingly, TSMC's N4X can potentially enable higher frequencies than even the company's next-generation N3 process.

One of the problems that is caused by shrinking sizes of transistors is shrinking sizes of their contacts, which means increased contact resistance and consequent problems with power delivery. Various manufacturers use different ways of tackling the contact resistance issue: Intel uses cobalt contacts instead of tungsten contacts, whereas other makers opted to forming contacts using selective tungsten deposition technology. While these methods work perfectly for pretty much all kinds of chips, there are still ways to further improve power delivery for high-performance computing (HPC) designs, which are relatively immodest about the total about of power/voltage being used. This is exactly what TSMC did to its N4X node. But before we proceed to details about the new fabrication process, let us see what advantages TSMC promises with it. 

TSMC claims that its N4X node can enable up to 15% higher clocks compared to a similar circuit made using N5 as well as an up to 4% higher frequency compared to an IC produced using its N4P node while running at 1.2V. Furthermore – and seemingly more important – N4X can achieve drive voltages beyond 1.2V to get even higher clocks. To put the numbers into context: Apple's M1 family SoCs made at N5 run at 3.20 GHz, but if these SoCs were produced using N4X, then using TSMC's math they could theoretically be pushed to around 3.70 GHz or at an even higher frequency at voltages beyond 1.2V.

TSMC does not compare transistor density of N4X to other members of its N5 family, but normally processors and SoCs for HPC applications are not designed using high-density libraries. As for power, drive voltages of over 1.2V will naturally increase power consumption compared to chips produced using other N5-class nodes, but since the node is designed for HPC/datacenter applications, its focus is to provide the highest performance possible with power being a secondary concern. In fact, total power consumption has been increasing on HPC-class GPUs and similar parts for the last couple of generations now, and there is no sign this will stop in the next couple of generations of products, thanks in part to N4X.

"HPC is now TSMC's fastest-growing business segment and we are proud to introduce N4X, the first in the ‘X’ lineage of our extreme performance semiconductor technologies," said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. "The demands of the HPC segment are unrelenting, and TSMC has not only tailored our ‘X’ semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric advanced packaging technologies to offer the best HPC platform."

In a bid to increase performance and make drive voltages of over 1.2V possible, TSMC had to evolve the entire process stack.

• First, it redesigned its FinFET transistors and optimized them both for high clocks and high drive currents, which probably means reducing resistance and parasitic capacitance and boosting the current flow through the channel. We do not know whether it had to increase gate-to-gate pitch spacing and at this point TSMC does not say what exactly it did and how it affected transistor density.
• Secondly, it introduced new high-density metal-insulator-metal (MiM) capacitors for stable power delivery under extreme loads.
• Thirdly, it redesigned back-end-of-line metal stack to deliver more power to transistors. Again, we do not know how this affected transistor density and ultimately die sizes.

To a large degree, Intel introduced similar enhancements to its 10nm Enhanced SuperFin (now called Intel 7) process technology, which is not surprising as these are natural methods of increasing frequency potential.

What is spectacular is how significantly TSMC managed to increase clock speed potential of its N5 technology over time. A 15% increase puts N4X close to its next-generation N3 fabrication technology. Meanwhile, with drive voltages beyond 1.2V, this node will actually enable higher clocks than N3, making it particularly good for datacenter CPUs.

TSMC says that expects the first N4X designs to enter risk production by the first half of 2023, which is a very vague description of timing, as it may mean very late 2022 or early 2023. In any case, it usually takes a year for a chip to proceed from risk production to high-volume production iteration, so it is reasonable to expect the first N4X designs to hit the market in early 2024. This is perhaps a weakness of N4X as by the time its N3 will be fully ramped and while N4X promises to have an edge in terms of clocks, N3 will have a major advantage in terms of transistor density.

Source: TSMC