TSMC has introduced a brand-new manufacturing technology roughly every two years over the past decade. Yet as the complexity of developing new fabrication processes is compounding, it is getting increasingly difficult to maintain such a cadence. The company has previously acknowledged that it will start producing chips using its N3 (3 nm) node about four months later than the industry is used to (i.e., Q2), and in a recent conference call with analysts, TSMC revealed additional details about its latest process technology roadmap, focusing on their N3, N3E, and N2 (2 nm) technologies.

N3 in 2023

TSMC's N3 technology will provide full node scaling compared to N5, so its adopters will get all performance (10% - 15%), power (-25% ~ -30%), and area (1.7x higher for logic) enhancements that they come to expect from a new node in this day and age. But these advantages will come at a cost. The fabrication process will rely extensively on extreme ultraviolet (EUV) lithography, and while the exact number of EUV layers is unknown, it will be a greater number of layers than the 14 used in N5. The extreme complexity of the technology will further add to the number of process steps – bringing it toto well over 1000 – which will further increase cycle times. 

As a result, while mass production of the first chips using TSMC's N3 node will begin in the second half of 2022, the company will only be shipping them to an undisclosed client for revenue in the first quarter of 2023. Many observers, however, expected these chips to ship in late 2022.

"N3 risk production is scheduled in 2021, and production will start in second half of 2022," said C.C. Wei, CEO of TSMC. "So second half of 2022 will be our mass production, but you can expect that revenue will be seen in first quarter of 2023 because it takes long — it takes cycle time to have all those wafer out."

N3E in 2024

Traditionally, TSMC offers performance-enhanced and application-specific process technologies based on its leading-edge nodes several quarters after their introduction. With N3, the company will be changing their tactics somewhat, and will introduce a node called N3E, which can be considered as an enhanced version of N3. 

This process node will introduce an improved process window with performance, power, and yield enhancements. It is unclear whether N3 meets TSMC's expectations for PPA and yield, but the very fact that the foundry is talking about improving yields indicates that there is a way to improve it beyond traditional yield boosting methods. 

"We also introduced N3E as an extension of our N3 family," said Wei. "N3E will feature improved manufacturing process window with better performance, power and yield. Volume production of N3E is scheduled for one year after N3."

TSMC has not commented on whether N3E will be compatible with N3's design rules, design infrastructure, and IPs. Meanwhile, since N3E will serve customers a year after N3 (i.e., in 2024), there will be quite some time for chip designers to prepare for the new node.

N2 in 2025

TSMC's N2 fabrication process has largely been a mystery so far. The company has confirmed that it was considering gate-all-around field-effect transistors (GAAFETs) for this node, but has never said that the decision was final. Furthermore, it has never previously disclosed a schedule for N2. 

But as N2 gets closer, TSMC is slowly locking down some additional details. Particularly, the company is now formally confirming that the N2 node is scheduled for 2025. Though they are not elaborating on whether this means HVM in 2025, or shipments in 2025.

"I can share with you that in our 2-nm technology, the density and performance, will be the most competitive in 2025," said Wei.