TSMC has quietly introduced a performance-enhanced version of its 7 nm DUV (N7) and 5 nm EUV (N5) manufacturing process. The company’s N7P and N5P technologies are designed for customers that need to make then 7 nm designs run faster, or consume slightly lower amount of power.

TSMC’s N7P uses the same design rules as the company’s N7, but features front-end-of-line (FEOL) and middle-end-of-line (MOL) optimizations that enable to either boost performance by 7% at the same power, or lower power consumption by 10% at the same clocks. The process technology is already available to TSMC customers, the contract maker of chips revealed at the 2019 VLSI Symposium in Japan, yet the company does not seem to advertise it broadly.

N7P uses proven deep ultraviolet (DUV) lithography and does not offer any transistor density improvements over N7. Those TSMC clients that need a ~ 18~20% higher transistor density are expected to use N7+ and N6 process technologies that use extreme ultraviolet (EUV) lithography for several layers.

While both N7 and N6 will be ‘long’ nodes that will be used for years to come, TSMC’s next major node with substantial density, power, and performance improvements is N5 (5 nm). The latter will also be offered in a performance-enhanced version called N5P. This technology will also feature FEOL and MOL optimizations in order to make the chips run 7% faster at the same power, or reduce consumption by 15% at the same clocks.

Related Reading:

• TSMC: Most 7nm Clients Will Transition to 6nm
• TSMC Reveals 6 nm Process Technology: 7 nm with Higher Transistor Density
• TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready
• TSMC: 7nm Now Biggest Share of Revenue
• TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
• TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains
• Intel Details Manufacturing through 2023: 7nm, 7+, 7++, with Next Gen Packaging

Source: WikiChip.Org