As of late, the pursuit for higher resolutions, faster refresh rates, better contrasts, higher brightness, and more colors in displays, has created bandwidth demands that are pushing the limits of current interface standards. With that in mind, VESA has already announced DisplayPort 1.4’s successor to have double the bandwidth of 1.4.

From the side of mitigating bandwidth demands with data compression, a little over four years ago, VESA and the MIPI Alliance developed and released the first iteration of their Display Stream Compression (DSC) standard, a visually lossless codec intended to reduce the amount of transmitted image data. But where high-end external displays have much leeway in regards to power consumption and system design, the same cannot be said for mobile and embedded devices looking to incorporate the latest premium display technologies.

It is for this mobile and embedded space that today VESA and MIPI are formally announcing the VESA Display Compression-M v1.1 (VDC-M) standard, which was first mentioned at MWC2018. Slotting in as VESA’s third compression standard after DSC 1.1 (2014) and DSC 1.2 (2017), VDC-M 1.1 focuses on smartphones and other similarly embedded mobile display applications. At the expense of higher circuit complexity and no DSC 1.1 backwards compatibility, VDC-M offers a 5:1 compression ratio (4:1 for 24 bit color) as opposed to DSC’s 3.75/3:1 compression, but at the same visually lossless quality. In other words, VDC-M allows compression of 30-bit or 24-bit images down to 6 bits per pixel (bpp), while claiming “visually lossless viewing with no attendant loss of bandwidth” based on commissioned testing by York University.

Historically-speaking, VDC-M is more in-line with the mobile/laptop-oriented DSC 1.1, which has been publicly adopted into MIPI’s DSI 1.2 and DSI-2 1.0 standards, as well as VESA’s embedded DisplayPort (eDP) 1.4b. Though to be clear, for VDC-M, VESA is optimizing the codec for smartphones as opposed to the laptop-inclusive DSC 1.1/eDP 1.4, and isn't currently being worked into the eDP specification, instead featuring solely with DSI-2 1.1 for the time being. With the primary goals of increasing battery life, reducing form factor, and decreasing cost, much of these benefits will be driven with the codec reducing the video interface data rate by lowering clockspeeds.

At a high level, VDC-M allows system designers to reduce the link clock rate in order to lower system power, or alternatively opt to increase resolution and/or color bit depth using the same display interface. With compression, manufacturers can also reduce the number of interface wires, interconnects, and other connectors. In turn, these can lessen frame buffer load for video memory. VESA is pointing to these possibilities as methods of tuning power, weight/z-height, and system cost for mobile devices while still providing the needed display bandwidth. VESA notes that equalization requirements result in high speed interfaces consuming power at both TX (transmit) and RX (receive) ends.

The exact details of the added circuit complexity can be found in the public VDC-M standard documentation, but in short, there are some additional logic blocks necessary for the higher degree of compression. These include a 2 x 8 discrete cosine transform, a 2-line buffer for read-and-store of 2 x 8 blocks for the next block’s vertical prediction process, and a 4-stream multiplexer for achieving 4 pixels/clock decoding. And where DSC decoders require additional complexity for certain mode decision processing, VDC-M signals the modes used in each block. As usual, designers will be able to estimate design complexity from the open C source code.

While VDC-M is VESA’s latest display compression standard, it largely operates in a different sphere to the fairly recent DSC 1.2, which is not only designed for maximizing resolutions on external displays but also largely unavailable to consumers; DSC 1.2 support is included in DisplayPort 1.4, as well as the competing HDMI 2.1, but consumer-ready devices and displays conforming to either standard are not due for some time. In the meantime, existing interfaces require adjustments like 4:2:2 chroma subsampling to push ultra-high resolutions at ultra-high refresh rates (e.g. 4K at 144Hz).

On the MIPI Alliance side, they are publicly announcing DSI-2 v1.1 today, which incorporates the VDC-M standard into the DSI-2 transport layer. As DSC-2 already supports DSC, manufacturers will be able to choose either codec as desired. Additionally, Hardent has announced upcoming availability of VDC-M encoder and decoder blocks.

More information on VDC-M and VESA’s display stream compression codecs can be found on their site. Like DSC, VDC-M is a publicly open specification and is available in full on VESA's site. York University will present their DSC and VDC-M evaluation at Display Week 2018 next week.

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