Samsung this week announced that it had started mass production of its second-generation HBM2 memory code-named “Aquabolt”. The new memory devices have 8 GB capacity and operate at 2.4 Gbps data rate per pin. To hit the new data rate, Samsung had to apply new technologies related to TSV design and thermal control. Samsung intends to offer the new memory to customers for use in next-gen HPC, AI and graphics solutions.

General architecture of Samsung’s new 8 GB HBM2 “Aquabolt” memory is similar to the company’s previous-gen 8 GB HBM2 “Flarebolt” devices: each KGSDs (known good stacked die) is comprised of eight 8-Gb memory ICs (integrated circuits) interconnected using TSVs (through silicon vias) in an 8-Hi stack configuration. Every KGSD features a 1024-bit bus and with a 2.4 Gbps per pin data rate, it can offer up to 307.2 GB/s of memory bandwidth per stack.

When JEDEC published the HBM2 specification about two years ago, the spec only discussed three different speed bins for this type of memory —1 Gbps, 1.6 Gbps and 2.0 Gbps at 1.2 V for core and I/O — in context of timing parameters. Manufacturers are free to offer other speed bins and then developers of actual products can clock HBM2 memory in accordance with their own requirements for performance and power consumption. Meanwhile, standard HBM2 packages are offered with 1.6 Gbps and 2.0 Gbps speed bins (their actual clocks are 800 MHz and 1 GHz, respectively). It is noteworthy that to hit 2 Gbps, Samsung had to increase HBM2 voltages to 1.35 V, which is beyond what the spec allows, but so are realities of mass production.

Samsung’s new Aquabolt products operate at 2.4 Gbps, which is higher than the standard was designed for. Meanwhile, it seems that all the other parameters of the new HBM2 “Aquabolt” memory are perfectly within the spec. Moreover, Samsung’s new memory even lowers its voltage back to 1.2 V as a result of internal optimizations.

To increase actual memory frequency to 1.2 GHz and decrease voltage to 1.2 V at the same time, Samsung had to apply a new method to reduce collateral clock interference between the 5000+ TSVs. Samsung says that to lower the clock skew it had to decrease the deviation of data transfer speeds among the TSVs, but does not go beyond that. In addition, the company increased the number of thermal bumps between the DRAM dies to distribute heat more evenly across each KGSD and thus better dissipate it. Finally, Samsung’s Aquabolt HBM2 products feature an additional protective layer at the bottom to increase the physical strength of the package. It is unknown whether the strengthening had an impact on mechanical characteristics of KGSDs, but this is a possibility.

Makers of memory usually announce mass production of new DRAMs after they complete production the first batch, so the HBM2 Aquabolt memory from Samsung might already exist in more or less mass quantities. Now, it is up to Samsung’s partners to use the new KGSDs in their products.

It is noteworthy that SK Hynix also has 2.4 Gbps HBM2 chips slated for Q1 availability in its product catalog. It is up to SK Hynix to make appropriate announcements, but it looks like Samsung is not going to be alone with fast HBM2 packages in the coming months.

Related Reading:

• Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand
• JEDEC Publishes HBM2 Specification as Samsung Begins Mass Production of Chips
• SK Hynix: Customers Willing to Pay 2.5 Times More for HBM2 Memory
• Hot Chips 2016: Memory Vendors Discuss Ideas for Future Memory Tech - DDR5, Cheap HBM, & More