Yep, while we may not see as many of them in use with future DDR generations, you'd be a fool to believe we won't still see them for generations to come, even if they're stuck with older DDR specifications. Inertia is difficult to overcome and JIT manufacturing hasn't taken over the entire industry.
Also, the socket could always be repurposed for AI/Accelerators or various other purposes. Probably not on a budget laptop line, but who knows the future? Should be faster and lower latency than PCI-ex.
I was hoping for a denser form factor for next-gen DIMM replacement to accommodate smaller space on the motherboard while maintaining everything required for faster clocks and lower latency.
Probably need to wait for DDR6 for anything radical. CAM is a result of the SODIMM physical interface hitting a wall on one hand, and laptop makers trying to split the difference between thinner soldiered ram designs and the lower number of mobo variants from socketed designs.
I don't get it. Why is it advantageous to buffer the clock signal without buffering the command/address signals? They run at the same frequency and are distributed to all the chips in the same way; wouldn't they be subject to the exact same signal integrity issues as the clock is?
The diagram shows the existence of a PLL. It will provide a fine adjust of the phase lead/lag relationship between clock and data. And may also multiply up the clock frequency too - Allowing a slower external clock source. The computer will set the PLL's adjustments via the I2C comms link.
And there's a simple reason why Registered(Buffered) DIMMs are not in the design. It increases latency in both directions! Servers prioritise reliability and so RDIMMs are the norm there but rule of thumb is less buffering is going to be the more responsive solution.
>Why is it advantageous to buffer the clock signal without buffering the command/address signals?
Each chip only gets its address pins not all the other chip's, so you don't have the same fan out problem. IIRC DDR5 can run the command bus at half the data bus, so probably that is done here to avoid having to buffer the command bus, which would add additional latency.
Data also not buffered, in the registered sense. Only the clock is getting treatment, and that's to add the PLL. Any effective buffering of the clock is incidental.
So stupid question (maybe I missed in the article) but are these a drop-in upgrade in existing systems ? Or is something needed like new BIOS or CPU firmware upgrade ?
paragraph 4: "The new DIMMs will also be drop-in compatible with existing platforms (at least on paper), using the same 288-pin connector as today's standard DDR5 UDIMM"
The signalling is the same, just faster than supposed by JEDEC. That means you'll be overclocking your memory bus to use them (just like with any other enthusiast ram); but buffering the clock line should make hitting higher speeds while remaining stable a bit easier.
Embedding a local clock in the memory along with a PLL is an excellent choice. As an improvement: If there is ECC data generated and sent upstream to the CPU to check received data, this could potentially be scaled up to much higher speeds. The memory/CPU structure can self tune to run at the maximum safe speed. I believe they could also just move the memory data over PCIe lanes with that structure.
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III-V - Friday, June 21, 2024 - link
That soldering job on the CSODIMM...Terry_Craig - Friday, June 21, 2024 - link
More expensive RAM modules? I got it.ballsystemlord - Friday, June 21, 2024 - link
Why a big O with a dot in the center on the chip?It also would have been cool to see which CKD chip they're using is the picture, but the camera angle wasn't right.
Terry_Craig - Friday, June 21, 2024 - link
https://www.montage-tech.com/Memory_Interface/M88D...This is underlined in the caption below.
ballsystemlord - Saturday, June 22, 2024 - link
Thanks!1_rick - Friday, June 21, 2024 - link
The big O is a sticker covering up a QFN chip so we can't see what it is.Ryan Smith - Friday, June 21, 2024 - link
And just to be clear, that's the PMIC underneath.nandnandnand - Friday, June 21, 2024 - link
"So along with the CUDIMM, we'll have the Clocked SODIMM (CSODIMM)"I thought we were ditching SODIMM. Why bother enhancing it if it can't reach those higher speeds?
Ryan Smith - Friday, June 21, 2024 - link
While SODIMMs are likely to go away, it won't be overnight. As they're still a part of the DDR5 standard, some manufacturers will be sticking to them.Now I don't expect to see them around for DDR6, on the other hand (though I may yet live to eat those words).
HaninAT - Wednesday, July 3, 2024 - link
Yep, while we may not see as many of them in use with future DDR generations, you'd be a fool to believe we won't still see them for generations to come, even if they're stuck with older DDR specifications. Inertia is difficult to overcome and JIT manufacturing hasn't taken over the entire industry.Also, the socket could always be repurposed for AI/Accelerators or various other purposes. Probably not on a budget laptop line, but who knows the future? Should be faster and lower latency than PCI-ex.
lorribot - Friday, June 21, 2024 - link
"only three of them demonstrated their CUDIMMs at Computex. Of those four,"Some numbering problems at the end there.
Xajel - Saturday, June 22, 2024 - link
I was hoping for a denser form factor for next-gen DIMM replacement to accommodate smaller space on the motherboard while maintaining everything required for faster clocks and lower latency.DanNeely - Wednesday, June 26, 2024 - link
Probably need to wait for DDR6 for anything radical. CAM is a result of the SODIMM physical interface hitting a wall on one hand, and laptop makers trying to split the difference between thinner soldiered ram designs and the lower number of mobo variants from socketed designs.Dolda2000 - Saturday, June 22, 2024 - link
I don't get it. Why is it advantageous to buffer the clock signal without buffering the command/address signals? They run at the same frequency and are distributed to all the chips in the same way; wouldn't they be subject to the exact same signal integrity issues as the clock is?evanh - Sunday, June 23, 2024 - link
The diagram shows the existence of a PLL. It will provide a fine adjust of the phase lead/lag relationship between clock and data. And may also multiply up the clock frequency too - Allowing a slower external clock source. The computer will set the PLL's adjustments via the I2C comms link.evanh - Sunday, June 23, 2024 - link
Yeah, so that little box named PLL is hiding a lot of high performance configurable analogue functionality.evanh - Sunday, June 23, 2024 - link
And there's a simple reason why Registered(Buffered) DIMMs are not in the design. It increases latency in both directions! Servers prioritise reliability and so RDIMMs are the norm there but rule of thumb is less buffering is going to be the more responsive solution.saratoga4 - Sunday, June 23, 2024 - link
>Why is it advantageous to buffer the clock signal without buffering the command/address signals?Each chip only gets its address pins not all the other chip's, so you don't have the same fan out problem. IIRC DDR5 can run the command bus at half the data bus, so probably that is done here to avoid having to buffer the command bus, which would add additional latency.
evanh - Monday, June 24, 2024 - link
Data also not buffered, in the registered sense. Only the clock is getting treatment, and that's to add the PLL. Any effective buffering of the clock is incidental.haplo602 - Monday, June 24, 2024 - link
So stupid question (maybe I missed in the article) but are these a drop-in upgrade in existing systems ? Or is something needed like new BIOS or CPU firmware upgrade ?kn00tcn - Monday, June 24, 2024 - link
paragraph 4: "The new DIMMs will also be drop-in compatible with existing platforms (at least on paper), using the same 288-pin connector as today's standard DDR5 UDIMM"haplo602 - Tuesday, June 25, 2024 - link
same connector does not mean compatibility if the signalling is different ...DanNeely - Wednesday, June 26, 2024 - link
The signalling is the same, just faster than supposed by JEDEC. That means you'll be overclocking your memory bus to use them (just like with any other enthusiast ram); but buffering the clock line should make hitting higher speeds while remaining stable a bit easier.evanh - Wednesday, June 26, 2024 - link
To make use of full potential will need a firmware update, yes.Chuck_NC - Tuesday, June 25, 2024 - link
Embedding a local clock in the memory along with a PLL is an excellent choice. As an improvement: If there is ECC data generated and sent upstream to the CPU to check received data, this could potentially be scaled up to much higher speeds. The memory/CPU structure can self tune to run at the maximum safe speed. I believe they could also just move the memory data over PCIe lanes with that structure.TMDDX - Thursday, June 27, 2024 - link
Not to be confused with a Romulan Cloaked UDIMM