Siena almost surely won't be on the massive SP5 socket. It'll basically for SURE be on the smaller SP3-sized SP6 socket (aka the same socket next-gen Threadripper Pro will inevitably use). Hence the "lower cost platform".
'.... SP5 socket (LGA6096), and will feature twelve memory channels'. Each DDR5 DIMM got two memory channels that are 32 bit wide. Does this mean that it just operates with 6 DIMMs in parallel? I would rather be informed how wide the memory connection is. I guess the possibilities are 384 bit or 768 bit. A DDR4 DIMM is one channel 64 bit wide, so SP3 is 8 * 64 bit = 512 bit.
No, 64/80-bit (ECC) DDR5 sticks doesn't have two channels, they have "two independent *sub-channels*" - check any DDR5 memory chip spec sheet if you don't believe me.
Some of the SP5/Genoa reports specifically mention 12 channels/24 sub-channels too, just to be safe even though it's not strictly speaking ambiguous.
Given that it's guaranteed to allow (and almost always use) ECC memory the physical memory interface isn't 64-bit per channel, it's 64/80-bit though only 64-bit ends up visible.
The reason why it needs 80-bit for ECC instead of 72-bit like older DDR standards is due to these subchannels, since they're "independent" the ECC needs to be done on them individually so they're each 40-bit width to allow for SECDED correction.
You need a minimum of 7 extra bits for 32-bit SECDED, 8 bits is enough for 64-bit SECDED, so in theory they could have gone with 39-bit subchannels for DDR5 ECC but that made no sense - all DDR5 memory chips are either 4, 8 or 16-bit wide so "78-bit" wouldn't save anything.
I guess it will be the cause of some confusion with channels and sub-channels. In the announcement of AMD Ryzen 7000 on this website Gavin Bonshor write 'AM5 also brings quad-channel (128-bit) DDR5 support to AMD's platforms, which promises a significant boost in memory bandwidth'. Se https://www.anandtech.com/show/17399/amd-ryzen-700... in the section: 'AMD's AM5 Platform: Socket LGA1718 with Three New Chipsets.....'.
In this case I guess the author is talking about quad-subchannels.
That is correct the author is talking about the number of sub-channels. You will still calculate the bandwidth the same way. 8 (number of bytes in a 64bit channel) * <number of channels> * <RAM speed> = RAM Bandwidth
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boozed - Thursday, June 9, 2022 - link
"1GB (or more) of L3 cache per socket"Now we're talking!
ballsystemlord - Thursday, June 9, 2022 - link
Sadly, not for our PCs.Foeketijn - Saturday, June 11, 2022 - link
What site are we on? I used to run a dual P3 with 1Gb memory to run minesweeper extra fast.nandnandnand - Saturday, June 11, 2022 - link
The amount that a single core can use won't change between Genoa-X and Raphael-X. Still 96 MiB, same as the 5800X3D.Shorty_ - Thursday, June 9, 2022 - link
Can you confirm which socket Siena is on? I've heard quite a few rumours it'll be on SP4 not SP5 (which has fewer memory channels etc)Cooe - Friday, June 10, 2022 - link
Siena almost surely won't be on the massive SP5 socket. It'll basically for SURE be on the smaller SP3-sized SP6 socket (aka the same socket next-gen Threadripper Pro will inevitably use). Hence the "lower cost platform".Andresen - Friday, June 10, 2022 - link
'.... SP5 socket (LGA6096), and will feature twelve memory channels'. Each DDR5 DIMM got two memory channels that are 32 bit wide. Does this mean that it just operates with 6 DIMMs in parallel? I would rather be informed how wide the memory connection is. I guess the possibilities are 384 bit or 768 bit. A DDR4 DIMM is one channel 64 bit wide, so SP3 is 8 * 64 bit = 512 bit.TLindgren - Friday, June 10, 2022 - link
No, 64/80-bit (ECC) DDR5 sticks doesn't have two channels, they have "two independent *sub-channels*" - check any DDR5 memory chip spec sheet if you don't believe me.Some of the SP5/Genoa reports specifically mention 12 channels/24 sub-channels too, just to be safe even though it's not strictly speaking ambiguous.
Given that it's guaranteed to allow (and almost always use) ECC memory the physical memory interface isn't 64-bit per channel, it's 64/80-bit though only 64-bit ends up visible.
The reason why it needs 80-bit for ECC instead of 72-bit like older DDR standards is due to these subchannels, since they're "independent" the ECC needs to be done on them individually so they're each 40-bit width to allow for SECDED correction.
You need a minimum of 7 extra bits for 32-bit SECDED, 8 bits is enough for 64-bit SECDED, so in theory they could have gone with 39-bit subchannels for DDR5 ECC but that made no sense - all DDR5 memory chips are either 4, 8 or 16-bit wide so "78-bit" wouldn't save anything.
Andresen - Tuesday, June 14, 2022 - link
Thanks for making it clear.I guess it will be the cause of some confusion with channels and sub-channels. In the announcement of AMD Ryzen 7000 on this website Gavin Bonshor write 'AM5 also brings quad-channel (128-bit) DDR5 support to AMD's platforms, which promises a significant boost in memory bandwidth'. Se https://www.anandtech.com/show/17399/amd-ryzen-700... in the section: 'AMD's AM5 Platform: Socket LGA1718 with Three New Chipsets.....'.
In this case I guess the author is talking about quad-subchannels.
schujj07 - Wednesday, June 15, 2022 - link
That is correct the author is talking about the number of sub-channels. You will still calculate the bandwidth the same way. 8 (number of bytes in a 64bit channel) * <number of channels> * <RAM speed> = RAM Bandwidth