Interesting design choice, MRAM up front as writce cache, but QLC at the back .I guess with a write cache like this you can really optimize Number of writes to QLC to prolong its life and it must be long enough cycling to last through the warranty period. Just seems odd to put expensive robust components in front of NAND that can be written to like only 300-400 times.
In another presentation at the FMS 2020, Brent Yardley was giving more details about how the MRAM is being used. It's main purpose is to act as a destage and journal buffer and holds flash firmware tables for data persistence during power loss. The MRAM size is tiny compared to the total Flash capacity and hence does not really contribute to reduce the writes to QLC. However, using the same flash blocks in either SLC or QLC mode in an intelligent way depending on workload properties combined with background calibration, strong ECC, and wear leveling techniques including health binning are the key contributors that prolong its life. The endurance of MRAM is orders of magnitudes higher than Flash.
Very late comment, but looking at the Micron 5210 ION series' TBW to capacity (which came to market early 2019) makes it obvious that Micron's QLC nand is specced to last at least ~1500 write cycles.
@BillyTallis - you seem to have an error/misreading. The IBM slide "FCM QLC Performs well" shows read latency CUT by up to 40% and write latency CUT by up to 33%. The article restates this (in the paragraph above the same slide) as the new NAND has 3x the write latency and 2-3 times the read latency. This doesn't stack up . Perhaps you're pulling background data and referring to the raw NAND flash performance but that's misleading in of itself & not relevant if the drive has the performance IBM claims on their slide: *reductions* of 40% & 33%.
The figures on the slide are referring to the drive's performance, which is improved despite the raw NAND being slower (when used as QLC rather than SLC).
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
5 Comments
Back to Article
cyrusfox - Thursday, November 12, 2020 - link
Interesting design choice, MRAM up front as writce cache, but QLC at the back .I guess with a write cache like this you can really optimize Number of writes to QLC to prolong its life and it must be long enough cycling to last through the warranty period. Just seems odd to put expensive robust components in front of NAND that can be written to like only 300-400 times.pletka - Thursday, November 12, 2020 - link
In another presentation at the FMS 2020, Brent Yardley was giving more details about how the MRAM is being used. It's main purpose is to act as a destage and journal buffer and holds flash firmware tables for data persistence during power loss. The MRAM size is tiny compared to the total Flash capacity and hence does not really contribute to reduce the writes to QLC. However, using the same flash blocks in either SLC or QLC mode in an intelligent way depending on workload properties combined with background calibration, strong ECC, and wear leveling techniques including health binning are the key contributors that prolong its life. The endurance of MRAM is orders of magnitudes higher than Flash.steamrick - Wednesday, January 12, 2022 - link
Very late comment, but looking at the Micron 5210 ION series' TBW to capacity (which came to market early 2019) makes it obvious that Micron's QLC nand is specced to last at least ~1500 write cycles.TimSyd - Thursday, November 12, 2020 - link
@BillyTallis - you seem to have an error/misreading. The IBM slide "FCM QLC Performs well" shows read latency CUT by up to 40% and write latency CUT by up to 33%. The article restates this (in the paragraph above the same slide) as the new NAND has 3x the write latency and 2-3 times the read latency. This doesn't stack up .Perhaps you're pulling background data and referring to the raw NAND flash performance but that's misleading in of itself & not relevant if the drive has the performance IBM claims on their slide: *reductions* of 40% & 33%.
Billy Tallis - Thursday, November 12, 2020 - link
The figures on the slide are referring to the drive's performance, which is improved despite the raw NAND being slower (when used as QLC rather than SLC).