Even with the high level of redundancy in the design, I am surprised that they get close to 100% yield, I would have expected a fatal error (eg a mask misalignment making an individual chip unusable) in a high proportion of wafers. From the earlier description on Anandtech, there is redundancy inside each chip but not between chips (ie a dead chip cannot be bypassed). There might have been a miscommunication is this article - what might have been meant is that each wafer supplied to customers is 100% functional not that every wafer produced in the Fab is functional.
M1 is pretty damn big in a patterning environment, and thats where youd see discontinuity. Its not so hard to not mess up patterning across a whole wafer at that scale.
Now down in the transistor layers where feature size is tiny? yeah, basically impossible
IIRC there are redundant chips on each row, so they can indeed bypass dead chips with the interconnect. I assume some healthy chips are sacrificed to get a rectangular array.
Also, its TSMC 16nm. Interconnect black magic aside, yields are probably pretty good by now.
100% yield in this case I think it means that every single wafer scale chip is functional. The percentage is probably variable, but they must have set the specs for this while taking into account the losses incured by defects on the wafer.
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Duncan Macdonald - Tuesday, June 9, 2020 - link
Even with the high level of redundancy in the design, I am surprised that they get close to 100% yield, I would have expected a fatal error (eg a mask misalignment making an individual chip unusable) in a high proportion of wafers. From the earlier description on Anandtech, there is redundancy inside each chip but not between chips (ie a dead chip cannot be bypassed).There might have been a miscommunication is this article - what might have been meant is that each wafer supplied to customers is 100% functional not that every wafer produced in the Fab is functional.
jbrukardt - Tuesday, June 9, 2020 - link
M1 is pretty damn big in a patterning environment, and thats where youd see discontinuity. Its not so hard to not mess up patterning across a whole wafer at that scale.Now down in the transistor layers where feature size is tiny? yeah, basically impossible
brucethemoose - Tuesday, June 9, 2020 - link
IIRC there are redundant chips on each row, so they can indeed bypass dead chips with the interconnect. I assume some healthy chips are sacrificed to get a rectangular array.Also, its TSMC 16nm. Interconnect black magic aside, yields are probably pretty good by now.
yeeeeman - Wednesday, June 10, 2020 - link
100% yield in this case I think it means that every single wafer scale chip is functional. The percentage is probably variable, but they must have set the specs for this while taking into account the losses incured by defects on the wafer.Spunjji - Monday, June 15, 2020 - link
That's the impression I got, too. Anything less would imply a painfully high cost for production.ritawgoodman12 - Thursday, June 18, 2020 - link
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Ian hungers for wafer!Oxford Guy - Wednesday, June 10, 2020 - link
How many wafers would it take to produce a perfect one, with not a single defect?Someone here said it's impossible but I don't agree. It has to be possible, however improbable.
FreckledTrout - Thursday, June 11, 2020 - link
LOL Ian you have to take the CPU out of its wrapper before you eat it.hafizmajid - Sunday, June 14, 2020 - link
No wonder we have a chip shortage, it Ian eating them allMonicaJB - Monday, June 15, 2020 - link
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