My first dozen or so machines had less RAM, and I've always overspent on RAM.
On a more interesting note, this tells me that AMD is willing to play with L3 cache configurations for the Zen platform. I wonder if Zen 3 will bring us varying levels of cache?
Zen 3 apparently ditches the CCX design (or makes the entire 8-core chiplet a "CCX" only in name) and unifies the L3 cache of the chiplet. This means that all 8 cores will have roughly the same latency when they access the entire L3 cache, which is the case with Intel's L3 cache - at least up to 8 or 10 cores - as well.
As a trade-off this scheme might limit the available cache options, though that would not affect Epyc. As we can see in the table of the article Epyc's L3 cache is available in multiples of 64 MB, i.e. the cache of a pair of chiplets. AMD could offer up to multiples of 32 MB, though that would arguably be quite an excessive .. cache variety.
Therefore, assuming Zen 3 will still have 32 MB of (unified) L3 cache per chiplet, even if that cache's size could not be configured (it probably will) that wouldn't matter to Epyc. What matters more is that the ditching of CCX will be a boon for multi-thread performance.
I believe Ryzen CPUs can't access L3 cache on other CCXes (each Zen 2 core only sees the CCX-local 16MB), so it would be true even today that "all cores have the same latency to the L3 (that they have access to)".
The Zen 2 L3 cache is comprised of 4 x 4MB slices, any number of which can be disabled so the theoretical flexibility is there already.
Zen 2 needs the 16MB L3 per CCX for performance reasons, because that's all each core will see. Once you combine two CCXes, it might make more sense to tone down the L3 size per die to something like 24MB in order to keep latencies in check (larger cache has higher latency). If the die ends up having 24MB+ of L3, all but the highest-end consumer parts could well have some of that fused off.
VIC-20 for me with RAM upgraded to 32KB that I got second hand after the previous owner purchased a new C64. Good times on that old clunker though the keyboard ergonimics left a lot to be desired. Compared to the manual typewriter I was using before that where my fingers once in a great while got stuck between the keys, it was an improvement.
32K? Luxury. I had only 4 or 8K in my first TRS-80. And by "my" I mean the display unit in the Tandy Electronics store I used to hang around in as a kid.
You can thank tsmc and especially apple for that. The 7nm process is a result of great r&d on tsmc part and a great partnership with apple, pushing them on moving faster to each node by providing the cash to buy equipment and give precious feedback for each node.
More cache means more chances that the CPU cores have the required data ready to go, hence faster execution. A lot of Zen 2 core weaknesses are hidden by this huge cache.
Remember that the L3 is part of the architecture. If the large cache helps alleviate "weaknesses" then they are no longer weaknesses. I know you just want to slander Zen2's performance, but the IPC advantage over Skylake is very, very real. Remember that Skylake Server parts have a Huge L2 cache per core (1MB) and the desktop parts in lightly threaded workloads can acccess the same amount of cache as Zen2 on desktop (9900K has 16MB, the same as in 1 Zen2 CCX). It's only really coming into play in heavy threaded workloads. Zen2 has the best x86 prefetchers and branch prediciton available on desktop, and is much wider than Skylake, too. The only "weakness" of the Zen2 design I can see versus Skylake is the higher raw memory latency, but it's using a chiplet design so Go figure.
Nailed it. Tired of people (Okay, mostly HStewart) pounding on this "Zen 2 only has good performance because it has lots of cache" non sequitur.
If cache was the key advantage, Intel would have already jammed more onto the third or fourth re-spin of Skylake. They haven't because they'd need to redesign the core to see any significant benefit.
Certainly an odd argument. It's like saying a Porsche 911 only goes as fast as it does due to the twin turbos that came with the engine. Imagine that.
I do hope AMD can get the latency worked out so once Zen3 lands they have a CPU that also looks good on the gaming charts next to Intel especially in very high FPS. That is really the only hold out and once they can pass Intel at very high FPS gaming it should change the average gamers perception.
While L1 and L2 are associated to a single core, the L3 cache is shared between all of them. So more cores -> more cache. L3 is used to share data between cores (useful for multi threaded applications) and reduces the need to load data from the much slower external RAM, while sharing information between multiple cores.
Seems unneccessary to diversify that line-up further.. i mean, are they aiming to have 8, 10, 12, 14, 16, 18, 20, 22, 24... 64 core versions .. with an immeasurable perf diff and $10 price difference..
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austinsguitar - Wednesday, February 19, 2020 - link
256MB of cache on a cpu... i had less in my first pc :) what i time to be alive man.austinsguitar - Wednesday, February 19, 2020 - link
less deditated wam. woopsFreckledTrout - Thursday, February 20, 2020 - link
LOL You need an edit button. -wamI had a 40MB hard drive in my first 286 PC.
eek2121 - Wednesday, February 19, 2020 - link
My first dozen or so machines had less RAM, and I've always overspent on RAM.On a more interesting note, this tells me that AMD is willing to play with L3 cache configurations for the Zen platform. I wonder if Zen 3 will bring us varying levels of cache?
Santoval - Wednesday, February 19, 2020 - link
Zen 3 apparently ditches the CCX design (or makes the entire 8-core chiplet a "CCX" only in name) and unifies the L3 cache of the chiplet. This means that all 8 cores will have roughly the same latency when they access the entire L3 cache, which is the case with Intel's L3 cache - at least up to 8 or 10 cores - as well.As a trade-off this scheme might limit the available cache options, though that would not affect Epyc. As we can see in the table of the article Epyc's L3 cache is available in multiples of 64 MB, i.e. the cache of a pair of chiplets. AMD could offer up to multiples of 32 MB, though that would arguably be quite an excessive .. cache variety.
Therefore, assuming Zen 3 will still have 32 MB of (unified) L3 cache per chiplet, even if that cache's size could not be configured (it probably will) that wouldn't matter to Epyc. What matters more is that the ditching of CCX will be a boon for multi-thread performance.
Hul8 - Wednesday, February 19, 2020 - link
I believe Ryzen CPUs can't access L3 cache on other CCXes (each Zen 2 core only sees the CCX-local 16MB), so it would be true even today that "all cores have the same latency to the L3 (that they have access to)".The Zen 2 L3 cache is comprised of 4 x 4MB slices, any number of which can be disabled so the theoretical flexibility is there already.
Zen 2 needs the 16MB L3 per CCX for performance reasons, because that's all each core will see. Once you combine two CCXes, it might make more sense to tone down the L3 size per die to something like 24MB in order to keep latencies in check (larger cache has higher latency). If the die ends up having 24MB+ of L3, all but the highest-end consumer parts could well have some of that fused off.
DanNeely - Wednesday, February 19, 2020 - link
The L1 cache on a cheap phone SoC has more ram than my first 2 computers.PeachNCream - Thursday, February 20, 2020 - link
VIC-20 for me with RAM upgraded to 32KB that I got second hand after the previous owner purchased a new C64. Good times on that old clunker though the keyboard ergonimics left a lot to be desired. Compared to the manual typewriter I was using before that where my fingers once in a great while got stuck between the keys, it was an improvement.prisonerX - Friday, February 21, 2020 - link
32K? Luxury. I had only 4 or 8K in my first TRS-80. And by "my" I mean the display unit in the Tandy Electronics store I used to hang around in as a kid.yeeeeman - Thursday, February 20, 2020 - link
You can thank tsmc and especially apple for that. The 7nm process is a result of great r&d on tsmc part and a great partnership with apple, pushing them on moving faster to each node by providing the cash to buy equipment and give precious feedback for each node.Irata - Thursday, February 20, 2020 - link
A good case of the trickle down effect actually working.AndrewPhilips - Wednesday, February 19, 2020 - link
What's the advantage of more cache?Supercell99 - Thursday, February 20, 2020 - link
faster p0rnyeeeeman - Thursday, February 20, 2020 - link
More cache means more chances that the CPU cores have the required data ready to go, hence faster execution. A lot of Zen 2 core weaknesses are hidden by this huge cache.AshlayW - Thursday, February 20, 2020 - link
Remember that the L3 is part of the architecture. If the large cache helps alleviate "weaknesses" then they are no longer weaknesses. I know you just want to slander Zen2's performance, but the IPC advantage over Skylake is very, very real. Remember that Skylake Server parts have a Huge L2 cache per core (1MB) and the desktop parts in lightly threaded workloads can acccess the same amount of cache as Zen2 on desktop (9900K has 16MB, the same as in 1 Zen2 CCX). It's only really coming into play in heavy threaded workloads. Zen2 has the best x86 prefetchers and branch prediciton available on desktop, and is much wider than Skylake, too. The only "weakness" of the Zen2 design I can see versus Skylake is the higher raw memory latency, but it's using a chiplet design so Go figure.Spunjji - Thursday, February 20, 2020 - link
Nailed it. Tired of people (Okay, mostly HStewart) pounding on this "Zen 2 only has good performance because it has lots of cache" non sequitur.If cache was the key advantage, Intel would have already jammed more onto the third or fourth re-spin of Skylake. They haven't because they'd need to redesign the core to see any significant benefit.
FreckledTrout - Thursday, February 20, 2020 - link
Certainly an odd argument. It's like saying a Porsche 911 only goes as fast as it does due to the twin turbos that came with the engine. Imagine that.I do hope AMD can get the latency worked out so once Zen3 lands they have a CPU that also looks good on the gaming charts next to Intel especially in very high FPS. That is really the only hold out and once they can pass Intel at very high FPS gaming it should change the average gamers perception.
Qasar - Thursday, February 20, 2020 - link
the only reason intel has any performance lead, is because of the high clocks, clock intel the same as zen 2, and they would looseQasar - Thursday, February 20, 2020 - link
it isnt hstewart that keeps saying that is gondalf..prisonerX - Friday, February 21, 2020 - link
There's a number of Intel shills on here. They're mostly butthurt stockholders who are bitter about holding Intel and not AMD.UpSpin - Thursday, February 20, 2020 - link
While L1 and L2 are associated to a single core, the L3 cache is shared between all of them. So more cores -> more cache. L3 is used to share data between cores (useful for multi threaded applications) and reduces the need to load data from the much slower external RAM, while sharing information between multiple cores.brunis.dk - Friday, February 21, 2020 - link
Seems unneccessary to diversify that line-up further.. i mean, are they aiming to have 8, 10, 12, 14, 16, 18, 20, 22, 24... 64 core versions .. with an immeasurable perf diff and $10 price difference..Qasar - Friday, February 21, 2020 - link
tell that to intel, how many variations of cpus does it have ???Korguz - Monday, February 24, 2020 - link
sounds like the " its ok if intel does it, but if amd does it, its completly wrong " mentality