This works well for core-to-core (or socket-to-socket) communications (let alone node-to-node), but eventually, it'll run into the biggest problem with HPC -- storage.
"Eventually", when storage becomes the bottleneck, non volatile memory could be used to replace NAND based SSDs, just as they are in the (long) process of replacing mechanical hard disks for almost all tasks except cold storage. Intel & Micron's 3D XPoint was a good start, but it's not as fast as (STT-)MRAM, for instance, which is faster even than DRAM and almost as fast as 6T-SRAM (still only at small sizes / low densities, unfortunately; MRAM starts to lose speed quickly at higher densities).
@Santoval : I agree with your view : there is a huge need for different low latency (less than 100ns) Non Volatile Memory (NVM) with a high enough density (probably at least GB) !!!
Regarding MRAM, there seems to be many different version of MRAM like STT-MRAM and SOT-MRAM.
I read some a (research) articles about work done by the Begium micro-electronic research center, IMEC about STT-MRAM / SOT-MRAM
My understanding is that STT-MRAM seems to have an access latency between approx. 1ns and 10ns, and SOT-MRAM access latency between approx 0.1ns and 1ns
Therefore the faster SOT-MRAM seems to be considered for L1 / L2 (and I would think L3) cache replacement, and STT-MRAM could be fit for L3 cache replacement / DRAM but seems not fast enough for L1/L2 cache.
Also it seems that IMEC has shown that a STT-MRAM (L3) cache seems to take less physical space that a SRAM cache at 5nm.
As of 2019, however, STT-MRAM is a more « mature » technology, and virtually all the biggest foundries (TSMC, Samsung, Globalfoundries) and also Intel seems to be working to introduce it in High Volume Manufacturing : so I have my fingers crossed that some innovative 5nm or below mobile SoC will apear on the market between H2 2020 (Apple A14 ?) and let say H2 2023 at latest : the sooner, the better as low latency NVM is key for real improvement to reduce / eliminate the painful latency of boot time / load time !!!
@Anton Shilov: My undestanding is that CXL / CCIX protocols are, at the moment, more intended for data-centers scenarii.
But, in theory, could it be possible to implement tje CXL (and also Gen-Z) protocols in a mobile SoC like for a future Qualcomm Snapdragon 875 that should be realeased around December 2020 / Qualcomm Snapdragon 885 (December 2021) ?
The goal would be to have a powerfull « generic » mobile SoC, to which could be attach different kind of chiplet accelerator (through CXL) / Storage Class Memory (SCM) (through Gen-Z) to easierly create different kind of mobile devices with different specialization ?
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alpha754293 - Friday, October 11, 2019 - link
This works well for core-to-core (or socket-to-socket) communications (let alone node-to-node), but eventually, it'll run into the biggest problem with HPC -- storage.Santoval - Saturday, October 12, 2019 - link
"Eventually", when storage becomes the bottleneck, non volatile memory could be used to replace NAND based SSDs, just as they are in the (long) process of replacing mechanical hard disks for almost all tasks except cold storage. Intel & Micron's 3D XPoint was a good start, but it's not as fast as (STT-)MRAM, for instance, which is faster even than DRAM and almost as fast as 6T-SRAM (still only at small sizes / low densities, unfortunately; MRAM starts to lose speed quickly at higher densities).Diogene7 - Saturday, October 12, 2019 - link
@Santoval : I agree with your view : there is a huge need for different low latency (less than 100ns) Non Volatile Memory (NVM) with a high enough density (probably at least GB) !!!Regarding MRAM, there seems to be many different version of MRAM like STT-MRAM and SOT-MRAM.
I read some a (research) articles about work done by the Begium micro-electronic research center, IMEC about STT-MRAM / SOT-MRAM
My understanding is that STT-MRAM seems to have an access latency between approx. 1ns and 10ns, and SOT-MRAM access latency between approx 0.1ns and 1ns
Therefore the faster SOT-MRAM seems to be considered for L1 / L2 (and I would think L3) cache replacement, and STT-MRAM could be fit for L3 cache replacement / DRAM but seems not fast enough for L1/L2 cache.
Also it seems that IMEC has shown that a STT-MRAM (L3) cache seems to take less physical space that a SRAM cache at 5nm.
As of 2019, however, STT-MRAM is a more « mature » technology, and virtually all the biggest foundries (TSMC, Samsung, Globalfoundries) and also Intel seems to be working to introduce it in High Volume Manufacturing : so I have my fingers crossed that some innovative 5nm or below mobile SoC will apear on the market between H2 2020 (Apple A14 ?) and let say H2 2023 at latest : the sooner, the better as low latency NVM is key for real improvement to reduce / eliminate the painful latency of boot time / load time !!!
Diogene7 - Friday, October 11, 2019 - link
@Anton Shilov: My undestanding is that CXL / CCIX protocols are, at the moment, more intended for data-centers scenarii.But, in theory, could it be possible to implement tje CXL (and also Gen-Z) protocols in a mobile SoC like for a future Qualcomm Snapdragon 875 that should be realeased around December 2020 / Qualcomm Snapdragon 885 (December 2021) ?
The goal would be to have a powerfull « generic » mobile SoC, to which could be attach different kind of chiplet accelerator (through CXL) / Storage Class Memory (SCM) (through Gen-Z) to easierly create different kind of mobile devices with different specialization ?