Big advantages of Windows for ARM (QuallComm) is that Lakefield does not have run applications in Emulation mode. Which likely the Tremont cores run faster than Windows for ARM.
I am curious is there a Windows for ARM emulator out there, Lakefield could probably run it faster
I guess you must have missed the recent benchmarks that show QC 8cx beat i5-8250U by a good margin both emulated and native while still giving twice the battery life...
And 68K to PPC. And reverse ARM to x86 (Project Catalyst). And 32-bit to 64-bit multiple times (PPC, then x86, then ARM). Most recently (Apple Watch) from 32-bit to 64-bit without even requiring recompilation.
Point is it CAN be done well and efficiently if the company wants it to be done that way. Of course MS still can't tell, 20+ years after .NET, what its strategy for byte code is... And it took forever to switch to Intel 64-bit. So, yeah, in the world of MS this may be more of an uphill battle. This is NOT an MS competence.
Note the 8cx CPU is twice as fast as the fastest Atom, so it can emulate x86 code faster than Atom can run it natively! So if you agree a modern Atom can run Windows well, the 8cx will be fast enough even when emulating.
This is a nice development from Intel. Not too afraid that it will give ARM problems, but it is a shame for a big company like Intel not to have some mobile devices in the era of mobile devices. I got it that in 2015 when they had the atom line mobile devices weren't so prevalent, but nowadays they are everywhere and they are starting to become good enough for most use cases. They need this development and they really need to have mobile products. I am pretty confident that they would sell, for the right price and performance.
The DRAM amount is highly limiting when even phones are going 16GB.
Foldable means high price, if it's a phone it needs integrated modem and if it's high price, it needs more DRAM and more than 1 big core. If it's a tablet, doesn't sell if as large as a phone, if much larger, the display costs stay insane for much longer as yields drop hard with area. Dual display is just moronic and costly. This is a solution for low end at best but do they have the costs to target low end? We'll see if they target something outside consumer but this first gen product doesn't seem to make much sense. If they were using ARM cores, it would have been a different matter, ARM offers so much more in terms of perf density.
I would expect that the 4G on chip is only part of the ran and probably have optional ram outside of chip. Also you got to think of type of device this is, this is not desktop gaming machine and these cores are likely significant faster than ARM cores.
"these cores are likely significant faster than ARM cores."
Which ARM cores? No way in hell even that SNC core is faster than an A12 Vortex... A76? Maybe, but A77 maybe not.
As for the 4GB, I think extra DRAM is unlikely. The mechanics become difficult -- two memory controllers and an additional set of DRAM pins? Go to Best Buy and look. A low end laptop (say $300 and lower) comes with 4GB.
My guess is that this is targeting things that are supposed to be iPad competitors, price maybe $200, crappy 64GB flash, no built in keyboard.
Maybe the OS will trap the SIGILL and fault AVX threads to the Sunny Cove core. Then, tag them as AVX-users to keep them off the Tremont cores. Still, that would be messed up, if code that's doing runtime checks for CPU instruction support has to keep checking, based on the core it's running on. Or you have a situation where all these threads have affinity for the big core and the Tremonts are just idling away.
So, I'm going to hazard a guess that either Tremont has AVX... or Sunny Cove doesn't.
It is certainly included (why would they redesign the Sunny Cove core just to remove the AVX-512 block?), but it might have been deactivated via firmware. Running AVX-512 code might blow up Lakefield's thermals well beyond 7W, unless perhaps the core was downclocked more than usual when running such code. The Tremont cores of course don't sport AVX-512, only the big Sunny Cove core might support it.
"Allows IPs to be developed independently, faster time to market"
This is the kind of nonsensical statement that Intel KEEPS making that makes me so dubious about them. It sounds good --- until you start to think about it...
So we have a partition between compute and support functionality. OK, good. And now I want to upgrade the support functionality, say from PCIe3 to PCIe4. OK, good. So with Foveros I design the PCIe4 circuits, create the masks, fab the new support chip, great. That's a certain level of time and verification. And suppose I was not using Foveros, but had a monolithic SoC. What would be involved? I design the PCIe circuits, create the masks, fab the new chip, great. WHERE is the EXTRA time and verification? What's making the Foveros path a faster time to market?
The PCIe circuits, whether on the SoC OR on a separate die, should be isolated from the rest of the functionality by well defined interfaces. Modifying them should be no different whether the modifications are on a full SoC chip, or on a separate chiplet. Everyone else in the world understands this --- that's ARM's entire fscking business model, that they sell you certain functionality as separate items (cores, GPU, memory controller, etc) that you mix and match on the same SoC. And this works because: well defined interfaces that isolate functionality.
Which gets us back to the Intel comment. How can we interpret it? - Intel has no clue how to isolate functionality on a SoC EXCEPT by putting it on separate chiplets. (Unlikely to be true, and terrifying if it is true...)
- Intel is flat out lying. This has zero to do with faster time to market (the rest of the world spins new SoCs, with massive upgraded functionality, every year -- doing so can be done if a company wants to do it). It's about, oh yes, 10nm yields. Keeping as much functionality as possible off 10nm as possible is necessary to ship anything in even small volumes.
Compare with AMD. AMD has chiplets because - it gives them optionality. They can sell a variety of different sizes, from 8 to 64 cores, without needing many different mask sets - once they have that optionality, under those circumstances it makes sense to do things like upgrade the IO chiplet separately
But Intel isn't playing that game. They aren't providing optionality with a range of LakeFields that provide 1, 2, up to 8 different Sunny Cove cores. Neither are they at anything close to the size limits where it ranges from expensive to impossible to create larger SoCs. It simply makes no sense to split a SoC in this way --- unless your process yield is abysmal...
"What this means for multiple workloads running at the same time"
Means that Intel REALLY cheaped out with providing only one large core... The performance implications are going to be obvious from the very first reviews. Which makes you wonder --- why?
The obvious conclusion is, once again, 10nm yield -- get that die size as small as possible! It's hard to know if that was the issue without being able to see the size of the SNC core relative to, eg, GPU. The other possibility is thermals. If SNC is just not that awesome in terms of watts generated (which seems plausible given how ICL is OK, but nothing spectacular, in that regard) then maybe two SNC's just can't be sustained in Foveros --- which seems, uh, problematic going forward...
(Thermal issues may not doom 3D stacking generally. TSMC seem confident about this, and they have a history of being reliable in their predictions. But Intel are stuck with their particular 10nm process, their particular design methodology --- chasing frequency rather than IPC --- and their details for Foveros --- exactly how things are bonded, exactly what thermal conduits are provided; and Intel's specifics for all of these are not TSMC's specifics.)
I wish more authors of this type of content would take the time you did to research and write so well. I am very impressed with your vision and insight. i'll suggest you all to check Geek Squad Support Phone Number visit https://www.errorcodeexpert.com/geek-squad-support... so you can resolve your all technical issue for home appliances or for a mac pro, television laptop etc.
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
28 Comments
Back to Article
voicequal - Tuesday, August 20, 2019 - link
Now if Intel would price it under $5 it could be the SoC for Raspberry Pi 5.Eris_Floralia - Tuesday, August 20, 2019 - link
LKF is for premium mobile. $500 maybe.HStewart - Thursday, August 22, 2019 - link
Big difference is Lakefield probably could emulate Raspberry PI.Eris_Floralia - Tuesday, August 20, 2019 - link
*P1222 is 22FFL used for base io dieToTTenTranz - Wednesday, August 21, 2019 - link
The purpose of this is to go against Windows on ARM?Love how the presenter's hatred of capital letters on slides is challenging Ian's OCD on the subject, BTW.
HStewart - Thursday, August 22, 2019 - link
Big advantages of Windows for ARM (QuallComm) is that Lakefield does not have run applications in Emulation mode. Which likely the Tremont cores run faster than Windows for ARM.I am curious is there a Windows for ARM emulator out there, Lakefield could probably run it faster
Wilco1 - Thursday, August 22, 2019 - link
I guess you must have missed the recent benchmarks that show QC 8cx beat i5-8250U by a good margin both emulated and native while still giving twice the battery life...https://www.tomshardware.co.uk/qualcomm-snapdragon...
But your indisputable love for Intel means you cannot accept hard facts.
HStewart - Thursday, August 22, 2019 - link
I was referring to x86 applications and according to the link provided"ARM native version of 3DMark Night Raid."
As a developer for 30 years, it takes a lot to port applications to new processor.
Korguz - Thursday, August 22, 2019 - link
Wilco1 " But your indisputable love for Intel means you cannot accept hard facts. " exactly !!!" As a developer for 30 years, " yea right, that's BS
Threska - Friday, August 23, 2019 - link
Apple's move to x86 from PowerPC.name99 - Wednesday, August 28, 2019 - link
And 68K to PPC. And reverse ARM to x86 (Project Catalyst).And 32-bit to 64-bit multiple times (PPC, then x86, then ARM).
Most recently (Apple Watch) from 32-bit to 64-bit without even requiring recompilation.
Point is it CAN be done well and efficiently if the company wants it to be done that way.
Of course MS still can't tell, 20+ years after .NET, what its strategy for byte code is... And it took forever to switch to Intel 64-bit.
So, yeah, in the world of MS this may be more of an uphill battle. This is NOT an MS competence.
Wilco1 - Friday, August 23, 2019 - link
The Office apps were not yet native AArch64 according to eg. https://www.windowscentral.com/snapdragon-8cx-benc...Note the 8cx CPU is twice as fast as the fastest Atom, so it can emulate x86 code faster than Atom can run it natively! So if you agree a modern Atom can run Windows well, the 8cx will be fast enough even when emulating.
efferz - Sunday, August 25, 2019 - link
my 8250U gets 7200 marks in Night Raid physics testefferz - Sunday, August 25, 2019 - link
If the 8250U only get 4400 marks，it may run at 2.1GHz.foxmusics - Saturday, August 31, 2019 - link
Well playedhttp://foxmusics.com/download-new-music/
yeeeeman - Wednesday, August 21, 2019 - link
This is a nice development from Intel. Not too afraid that it will give ARM problems, but it is a shame for a big company like Intel not to have some mobile devices in the era of mobile devices. I got it that in 2015 when they had the atom line mobile devices weren't so prevalent, but nowadays they are everywhere and they are starting to become good enough for most use cases. They need this development and they really need to have mobile products. I am pretty confident that they would sell, for the right price and performance.jjj - Wednesday, August 21, 2019 - link
The DRAM amount is highly limiting when even phones are going 16GB.Foldable means high price, if it's a phone it needs integrated modem and if it's high price, it needs more DRAM and more than 1 big core. If it's a tablet, doesn't sell if as large as a phone, if much larger, the display costs stay insane for much longer as yields drop hard with area.
Dual display is just moronic and costly.
This is a solution for low end at best but do they have the costs to target low end?
We'll see if they target something outside consumer but this first gen product doesn't seem to make much sense. If they were using ARM cores, it would have been a different matter, ARM offers so much more in terms of perf density.
HStewart - Thursday, August 22, 2019 - link
I would expect that the 4G on chip is only part of the ran and probably have optional ram outside of chip. Also you got to think of type of device this is, this is not desktop gaming machine and these cores are likely significant faster than ARM cores.name99 - Wednesday, August 28, 2019 - link
"these cores are likely significant faster than ARM cores."Which ARM cores? No way in hell even that SNC core is faster than an A12 Vortex...
A76? Maybe, but A77 maybe not.
As for the 4GB, I think extra DRAM is unlikely. The mechanics become difficult -- two memory controllers and an additional set of DRAM pins?
Go to Best Buy and look. A low end laptop (say $300 and lower) comes with 4GB.
My guess is that this is targeting things that are supposed to be iPad competitors, price maybe $200, crappy 64GB flash, no built in keyboard.
mode_13h - Wednesday, August 21, 2019 - link
So, will the Tremont cores get AVX or not?Maybe the OS will trap the SIGILL and fault AVX threads to the Sunny Cove core. Then, tag them as AVX-users to keep them off the Tremont cores. Still, that would be messed up, if code that's doing runtime checks for CPU instruction support has to keep checking, based on the core it's running on. Or you have a situation where all these threads have affinity for the big core and the Tremonts are just idling away.
So, I'm going to hazard a guess that either Tremont has AVX... or Sunny Cove doesn't.
HStewart - Thursday, August 22, 2019 - link
Sunny Cove supports AVX 512 - not sure if that is included in core on Lakefield or TremontSantoval - Thursday, August 22, 2019 - link
It is certainly included (why would they redesign the Sunny Cove core just to remove the AVX-512 block?), but it might have been deactivated via firmware. Running AVX-512 code might blow up Lakefield's thermals well beyond 7W, unless perhaps the core was downclocked more than usual when running such code. The Tremont cores of course don't sport AVX-512, only the big Sunny Cove core might support it.name99 - Wednesday, August 28, 2019 - link
"Allows IPs to be developed independently, faster time to market"This is the kind of nonsensical statement that Intel KEEPS making that makes me so dubious about them. It sounds good --- until you start to think about it...
So we have a partition between compute and support functionality. OK, good.
And now I want to upgrade the support functionality, say from PCIe3 to PCIe4. OK, good.
So with Foveros I design the PCIe4 circuits, create the masks, fab the new support chip, great. That's a certain level of time and verification.
And suppose I was not using Foveros, but had a monolithic SoC. What would be involved?
I design the PCIe circuits, create the masks, fab the new chip, great. WHERE is the EXTRA time and verification? What's making the Foveros path a faster time to market?
The PCIe circuits, whether on the SoC OR on a separate die, should be isolated from the rest of the functionality by well defined interfaces. Modifying them should be no different whether the modifications are on a full SoC chip, or on a separate chiplet. Everyone else in the world understands this --- that's ARM's entire fscking business model, that they sell you certain functionality as separate items (cores, GPU, memory controller, etc) that you mix and match on the same SoC. And this works because: well defined interfaces that isolate functionality.
Which gets us back to the Intel comment. How can we interpret it?
- Intel has no clue how to isolate functionality on a SoC EXCEPT by putting it on separate chiplets. (Unlikely to be true, and terrifying if it is true...)
- Intel is flat out lying. This has zero to do with faster time to market (the rest of the world spins new SoCs, with massive upgraded functionality, every year -- doing so can be done if a company wants to do it). It's about, oh yes, 10nm yields. Keeping as much functionality as possible off 10nm as possible is necessary to ship anything in even small volumes.
Compare with AMD.
AMD has chiplets because
- it gives them optionality. They can sell a variety of different sizes, from 8 to 64 cores, without needing many different mask sets
- once they have that optionality, under those circumstances it makes sense to do things like upgrade the IO chiplet separately
But Intel isn't playing that game. They aren't providing optionality with a range of LakeFields that provide 1, 2, up to 8 different Sunny Cove cores. Neither are they at anything close to the size limits where it ranges from expensive to impossible to create larger SoCs.
It simply makes no sense to split a SoC in this way --- unless your process yield is abysmal...
name99 - Wednesday, August 28, 2019 - link
"What this means for multiple workloads running at the same time"Means that Intel REALLY cheaped out with providing only one large core...
The performance implications are going to be obvious from the very first reviews.
Which makes you wonder --- why?
The obvious conclusion is, once again, 10nm yield -- get that die size as small as possible! It's hard to know if that was the issue without being able to see the size of the SNC core relative to, eg, GPU.
The other possibility is thermals. If SNC is just not that awesome in terms of watts generated (which seems plausible given how ICL is OK, but nothing spectacular, in that regard) then maybe two SNC's just can't be sustained in Foveros --- which seems, uh, problematic going forward...
(Thermal issues may not doom 3D stacking generally. TSMC seem confident about this, and they have a history of being reliable in their predictions. But Intel are stuck with their particular 10nm process, their particular design methodology --- chasing frequency rather than IPC --- and their details for Foveros --- exactly how things are bonded, exactly what thermal conduits are provided; and Intel's specifics for all of these are not TSMC's specifics.)
jvl - Friday, August 30, 2019 - link
Is it Lakefield, lakefield or lake field? Or LKF?Sewell5N - Wednesday, September 4, 2019 - link
Thanks for sharing this information <a href="https://ifacetimeapp.com/">ifacetimeapp<...Sewell5N - Wednesday, September 4, 2019 - link
Thanks for sharing this information https://ifacetimeapp.com/Cherryparker - Monday, September 16, 2019 - link
I wish more authors of this type of content would take the time you did to research and write so well. I am very impressed with your vision and insight. i'll suggest you all to checkGeek Squad Support Phone Number visit https://www.errorcodeexpert.com/geek-squad-support... so you can resolve your all technical issue for home appliances or for a mac pro, television laptop etc.