Great article. Very informative and highly impressed. These are the types of articles that keep me coming back to anandtech. Thanks very much. I hope the back side power delivery goes well for Intel, and from this article it appears that it will, also it’s nice to get that 6% frequency boost due to a change in power delivery. With the intel 4 M0 transistor gate pitch being 30nm, and with backside power delivery they made it 36nm. Really makes me wonder just how wide they need to keep these gate pitches, in the die shrinks, and just how many transistors per mm2 we are going to run up to, and where the point of shrink will stop.
As usual from an Intel presentation, you get an accurate (kinda...) story about what INTEL is doing, and a completely distorted story about how this relates to the rest of the world...
As far as the rest of the world goes https://www.imec-int.com/en/articles/imec-demonstr... Points being - imec (and through them, essentially TSMC and SS) have already demonstrated this tech in 2021. This includes Intel's precious nanoTSV's that they're trying hard to pretend are tech exclusive to them. What's known of TSMC is that their roadmap starts with BSPDN but NOT nano-TSV's, that's for a year later; but that reflects TSMC's usual caution, one step at a time; rather than they don't know about nTSV's or can't manufacture them.
- the big win with BSPDN is not the power/voltage droop improvements. Those are nice, but only matter if you're already driving your chip at crazy power levels. No, the big win is relieving routing congestion in M1. It is this routing congestion that has throttled the down-scaling of SRAM in recent processes; and the expectation is that by moving to BSPDN (even the initial, simpler, non-nTSV version chosen by TSMC for gen1) SRAM scaling can resume. BUT for that to be of value, you have to be willing to keep the rest of your metal network in place, as low-pitch as before...
In other words, the issue is not "Intel smart, TSMC stupid"; it is priorities. Intel's priority (for better or worse) it to be able to crank up the *effective* power and frequency of their chips even more. For them, right now, BSPDN matters insofar as it allows for slightly lower power translated into slightly higher clock. ISMC's priorities are (a) process implementation reliability [hence two stages, BSPDN first, nTSV second a year later] and (b) denser SRAM (which they get some of, even at the first stage of BSPDN without nTSV). IMHO the longer-term imec/TSMC strategy will also move clocks down to the backside. This will have little effect on power, but it will relieve routing even more, allowing for even denser SRAM. I have no idea, but I would not be surprised if at least part of the slow cautious TSMC strategy is to put together a process that naturally extends to moving the clocking layers to the backside, whereas the faster Intel strategy has been to ignore this and hope that, somehow, it can be retrofitted in the future...
Excellent post! Quite honestly this kind of balanced comparison of the various tech out there is what we would want in the main article. It’s a shame www.IntelTech.com hasn’t done this for a while now.
@name99 impressive post. I had been confused for some time about the limitation on scaling of SRAM as traditional 6T SRAM has only transisters which are scaling. Even DRAM with Capacitors is now scaling in production to 12 nm
At first it seem like what you talking about IMEC make a bit of sense. But the longer I read from other website and other things (of course a lot still not understand). But what I can conclude is now the following.
In July 2021, intel already mentioned a lot about PowerVIA, it that meant that your IMEC paper is in the same class, then TSMC is not behind. Sorry I don't get it.
Intel give us number and it also give us number of Intel 4 without PowerVIA, So now we can even draw some number out from TSMC N3 vs TSMC N5 vs Intel 4.
So the Contacted Gate Pitch is 45nm Vs 51nm Vs 50nm (lower is better). We know that there is only Single Digit Density improvement TSMC N3E Vs TSMC N5, we know that Intel 4 is at least better then TSMC N5, we know that Intel 4 Vs Intel 4 (with PowerVIA) bring double Digit Density with 6% free frequency boost through less noise and direct connect.
i.e. Intel 4 with PowerVIA beat both TSMC N3E and TSMC N5.
After I saw this from you, I am very worry about TSMC. Because I don't know whether TSMC N2 Vs TSMC N3E will bring single digit density boost (from another Anand Article), if you look at TSMC N2 Vs Intel 4 (with PowerVIA) then you can have the same density profile, that is very bad because we will not see TSMC N2 in another 2 years (2025). I didn't see any Risk Production on TSMC N2 Today, but Intel 4 (with PowerVIA) is at Risk Production stages.
On top you mentioned small steps, i.e. the First Backside Power Delivery might not even use nTSV and Intel PowerVIA meant that is TSMC 2nd Generation Backside Power Delivery.
In my point of view, I felt like that TSMC have all the resource (even more then Intel), they did not do a de-risk and produce a N3(Backside Power Delivery) (they have some many N3 Node name already (N3B/E/P/X) is is clear they can do a N3 (Backside Power Delivery Node), that is very bad for TSMC.
If Intel pull this off and just leave GAA just rename this Intel 4 PowerVia as Intel 20A, then they already fully catch up with TSMC. This is the fact.
What TSMC is doing sound like a company in trouble. 1) Quickly talk to their customer (probably with some price cut) and sell what it can - from what nVidia say they will use TSMC still. 2) Having buzz word and tell people they start procurement and process to start something that is remotely truth. (TSMC say that they start risk production of N2 but the road map show it is H2 2025 like 2 years away and for semi industry this is long for procurement purposes). 3) Having the CEO/CFO saying to analyst that the recent profit dip is temporary and having a good long term (financial tricks) (just like Bob Swam @ Intel), and not the CTO saying we have this tech and that tech so we are good. 4) No admitting this danger and just quick dive into the technology, i.e. have a N3 with backside power delivery, and not just focus on GAA, this is a mistake. The Intel slide show that it is cheap to manufacture Intel 4 with PowerVIA (2nd slides). 5) Your competitor is show you with hard numbers (Contacted Poly Pitch is very hard number and 95% density, people can scan your chip after it is available (meteor lake is 2H 2023), there is little room to cheat, and what you give in >1.15X over TSMC N3E (another article in Anand), so what is ">" meant about/around/best case????.
In other word it is an issue of Intel being smart and TSMC is stupid. This is a Trillion Dollar Company and this is what is happen after Chang left, I am very worry, just like when Paul Otellini and Pat left Intel (I really don't think Larrabee is a failure).
You seem to have missed that Intel is not introducing PowerVia until with 20A and thats half a year before TSMC N2, and looking back at the execution of process improvements the last 10 years between the two companies, Intel will likely still be behind, maybe a bit less but personally I doubt it.
That is the Pre Chang TSMC, post Chang TSMC missed N3B for at least 1 year, no one except Apple is going to use N3B, and the amount of EUV exposure in N3B is way too much, so they reduced in N3E (technically without any SRAM scaling vs N5, then N3E is just a name?). Looking at the post Chang record, I can also assume that TSMC N2P is only going to come out at 202X with delays on the card. CEO is long term planning guy, it was also not day 1 when Paul Otellini left and Intel shows the sinking, it take 3 years for us to know, CEO influence often shown 3+ years and guess what Chang retired 2018, and N3B problem is in 2022 (3/4 yearish).
Intel is already ahead (intel 4 is already 100% of what TSMC N3E High Performance is (3 Fins), the density side then intel did not show us or have High Density Library (2 Fins)), not behind you can be a cheerleader for TSMC, I was a TSMC shareholder and I sold that at 117 USD ADR and switch to ASML. With this intel slide, I am starting to switch from ASML to Applied Materials. I put real money to things that I talk, not a fanboy.
You can doubt it but the number 45nm Vs 51nm Vs 50nm, as far as I can see (because they all (all article from different source) say TSMC N3E will not bring density improvement over N5), might be this is not clear enough, it meant in the high performance library, TSMC N3E (next year) = Intel 4.
Intel is already 1 year ahead. As TSMC N3B is not a production ready node. Apple is consider go to N3E for iPhone 16. TSMC N3B with it's high number EUV layer + min density improve just not worth the cost. While Intel 4 with Applied Material help seem to crack to code, and their improve Intel 3 is next year, then that is second generation vs a first real N3 Class from TSMC.
They'll buy back more of their shares to pump the price a bit. Should have plenty of cash since they're getting that CHIPS Act money to pay for manufacturing upgrades.
Thermals are a mess. 30% of core area for thermal stuff? What's the benefit of backside power then (just 6% frequency?)? How is their "normalized" power and temperature compared to the regular Intel 4 chip? What was the size of the non backside Intel 4 chip?
At >> 10mm2 for 4 E-Core these E-cores are much bigger than regular E-Cores on Meteor Lake (we've seen die shot leaks)
Zero information... Please be more critical and ask these questions when you have the opportunity to directly talk to them instead of just posting their stuff.
BTW: They should've used P-cores instead of E-cores when it comes to thermals.
Like anybody from AT will attend VLSI Symposium and be able to ask meaningful questions...
VLSI Symposium is focusing on backside power/PowerVia this year, as every major foundry is offering it at the 2nm node (along with ribbon/GAA FET and some other advanced packaging techniques). Intel is going to present some details on their implementation. The focus is the improvement of power via alone, not how big the e-cores are compared to meteor lake.
You are missing the point of the article, the paper, and the content of VLSI Symposium this year. Go look at the program, then once the conference is done in a couple weeks go read the papers.
To be sure, we did have a chance to ask questions last week. But those ended up mostly centered around likes like the carrier wafer and wafer slimming, the E-cores, the defect rate, and EDA tools. There are always more questions than there is time to get them answered, at least initially.
The 30% of core area for thermals was to to insert redundant thermal monitors (+ trying several thermal monitoring techniques to find which performs better) and also to try out several special thermal mitigation techniques. One can only afford to do this on a test chip and the learnings will be incorporated in the products. The comment about 30% was to convey the point that the design team took the thermal seriously and spent "much area" on getting high quality and irrefutable thermal data and to also study the thermal sensitivities
For users + 6% higher clock, 12% higher density - harder to cool, may throttle decresaing clocks gain For Intel + lower cost for M0 - complex debug (higher cost for next gen cores design), more layers (additional cost despite easy to make), more silicon for carrier, additional costs for thinning and other processing
Overall not so beneficial, TSMC and Sansung have right not to rush with it until it is really needed.
The article states that Intel worked around the thermal issue with their design so harder to cool not so much. The shift in pitch is mostly about offsetting the additional costs so this also isn't so much a thing. If the pitch shift alone allows for them to drop one layer of multipatterning it has more than paid for itself.
Lower cost for M0, that is a big plus, this is where you needed EUV (Multiple patterning), the article is actually suggest is M1 layer having benefit.
Harder to cool? I think the backside power is mainly copper wires, and copper conduct heat well, look at your heat sink. Yes it can make it worst but I think the situation is not as bad as you guess.
complex debug? More Layers ??? negative for Intel not necessary, even if there are more layers if each layer become simpler then is actually easier to debug. You have power and signal cable tango each other. The layer is more simple.
TSMC and Samsung can say wherever they like but it can meant that TSMC and Samsung underestimate the technology.
If Intel can deliver on its promises, the company is expecting to be at least two years ahead of TSMC and Samsung in deploying backside power delivery – and that means at least two years of reaping the cost and performance benefits of the technology.
//
But that's only ahead of Intel's own nodes, whose performance isn't being detailed quite yet. Intel should pit their Intel 4 / Intel 3 / Intel PDN libraries onto an industry-standard core and even compare it to data for those same industry-standard cores at other fabs.
That's how you'd sell IDM 2.0 to investors & tech media (the only people that don't know this data already, but hold significant power over Intel's future).
Intel 3 production will be ready to begin mass production ramping soon. Power Via isn't supposed to be ready until 2024. Intel burned themselves badly in the past by putting too many new things into one basket and couldn't deliver. I can see why they waited another generation.
The process node used here (Intel 4 + PowerVia) is only for R&D purposes. It is not a production node. PowerVia won't go into production until Intel 20A.
Using Intel 3 as your base for the test node would have just made things take longer. Intel 3's advancements aren't pertinent to the development of BS-PDN.
(And if you're asking why Intel didn't make an Intel 3 + PowerVia production node, I point back to the fact that PowerVia won't be ready any earlier than in time for Intel 20A)
Not to skip too far ahead, but how will this impact GPU manufacturing?
Modern GPUs are already pushing thermal boundaries with 400-700w power draw. Having to extract that heat through additional layers of silicon seems very very challenging for those higher power/heat situations.
Because PowerVIA is a more efficient way to power the transistor (6% mentioned), you pump less amps into the transistor and will create less heat.
That clean power delivery, in turn, improves the compute performance and the energy efficiency of the chip. Besides the direct efficiency gains from losing less energy to resistance, constructing an E-core with PowerVia technology improved the maximum frequency (fMax) of the core by 6%. Intel doesn’t offer a more detailed explanation as to why this improved their clockspeeds, but I suspect it has to do with a higher voltage actually reaching the transistors themselves, allowing them to clock a bit higher. So you create 6% less heat in the first place, although we don't know how heat will leave the chip. We also don't know the structure of the dummy waffle, since before PowerVIA, the chip is package upside down and PowerVIA is the other way around, with the supportive dummy waffle on top. As heat goes up in physics, the structure/shape of the dummy waffle can be the difference to how heat is leaving the chip itself, are there holes in the dummy waffle, what is the shape of the holes, are those shape in anyway to help the heat leaving the chip, is the dummy waffle have a more heat conductive layer on top will that help the heat leaving the chip.
As Chip is moving from 2D to 2.5D/3D the mentioned joke about there are so little silicone left meaning that there are so many space(air) in between and where these spaces are will impact the heat leaving the chip.
From the article it read a follow: And while a 6% clockspeed uplift isn’t a massive gain, it’s essentially a “free” improvement coming from a technology that is designed to improve the manufacturability of a chip. Intel has worked harder to get smaller clockspeed improvements in the past.
Lower resistance isn't the only benefit of shorter, stouter, more direct power and ground connections provided by BS-PDN. Not mentioned, but every bit as significant, is lower inductance in the power paths. "Ground bounce" in signal return paths from excessive inductance can degrade signal switching margins, and thus frequency and performance. BS-PDN should help.
well all these gizmos and we are the best charts ,, innovative projects ,, on end we get hot chip that cant go head to head with zen ,and that need 6ghz 300w just to sit near same time pay different sites to bash amd epic which halt on 1000days reset and go again ,same time xeons die after 300-500h uptime just wow ,,,on end intel must have super pro chart guys same time ic designers/fab guys are meh
Looks like Intel is really gaining back their process lead vs TSMC in late 2024 timeframe. It's fascinating to see how many people doubted them even though they have the process lead for the longest time in history before they fumbled at 10nm. TSMC also fumbled many times before specially during the introduction of finfet. But they got back into competition over time and even took the lead. So, Intel taking back the lead is not really surprising specially at a time where TSMC is struggling with 3nm yield and delaying the introduction of backside PDN.
Samsung has been struggling with 3GAE (reported yields at 10-20%), TSMCs N3 started at similar levels as N5 at >70%, now over 80%, I think you mixed up the two companies and their processes. TSMC stated from the start that first N2 would only introduce GAA in 2025 and later versions would get BSPD, when did they delay it? Before Intel can get into the lead they need to catch up, they haven't shown that they can execute on that yet, but time will tell, it would be good if they can though as it seems Samsung continues to struggle to compete and it would be beneficial to have two competing foundries at the same level.
I haven't read all comments, maybe someone pointed it out already, but this tech is interesting also because, by having a very thin substrate after the polishing, they could in theory stack multiple dies on top of each other, so that no only wiring will be 3D (as it has been for decades) but also transistors, allowing closer proximity of related functionalities. It is done with memory on top of the die (AMD I don't remember the name), but stacking processing could also be interesting. Of course, for 2 layers the power wiring would end up on the outer sides, and in any case the chip may need cooling from both sides, so it could end up not as a pizza on top of the motherboard, but as a toaster with instead of heating from both sides of the bread, cooling from both sides.
Thanks for sharing this post! It's fascinating to see Intel's ambitious plans with PowerVia chip fabrication technology and RibbonFET for gate-all-around transistors. Considering the importance of these technologies in regaining their fab leadership position, Intel's R&D efforts must be at an all-time high. With the stakes so high, their progress in these areas becomes crucial not only for the company but for the entire industry.
The upcoming VLSI Symposium is undoubtedly going to be a significant event, drawing attention both inside and outside the company. As Intel moves closer to the production phase, presenting their findings on producing a complex logic test chip becomes a crucial milestone. This evidence of progress will be reassuring to investors and other outsiders, showing that Intel's efforts to get back on track are bearing fruit.
It's impressive to witness the culmination of years of hard work and research, which will eventually bring the "angstrom" era fab nodes into high volume manufacturing next year. Embracing these new technologies could propel Intel forward and potentially position them ahead of the competition, as they venture into the contract chip manufacturing business.
In conclusion, Intel's advancements in chip manufacturing technology are vital for the future of the company and the industry as a whole. We eagerly await the outcomes of the upcoming symposium and wish Intel the best in their journey towards technological excellence.
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DaRagingLunatic - Monday, June 5, 2023 - link
Great article. Very informative and highly impressed. These are the types of articles that keep me coming back to anandtech. Thanks very much. I hope the back side power delivery goes well for Intel, and from this article it appears that it will, also it’s nice to get that 6% frequency boost due to a change in power delivery. With the intel 4 M0 transistor gate pitch being 30nm, and with backside power delivery they made it 36nm. Really makes me wonder just how wide they need to keep these gate pitches, in the die shrinks, and just how many transistors per mm2 we are going to run up to, and where the point of shrink will stop.name99 - Monday, June 5, 2023 - link
As usual from an Intel presentation, you get an accurate (kinda...) story about what INTEL is doing, and a completely distorted story about how this relates to the rest of the world...As far as the rest of the world goes
https://www.imec-int.com/en/articles/imec-demonstr...
Points being
- imec (and through them, essentially TSMC and SS) have already demonstrated this tech in 2021. This includes Intel's precious nanoTSV's that they're trying hard to pretend are tech exclusive to them. What's known of TSMC is that their roadmap starts with BSPDN but NOT nano-TSV's, that's for a year later; but that reflects TSMC's usual caution, one step at a time; rather than they don't know about nTSV's or can't manufacture them.
- the big win with BSPDN is not the power/voltage droop improvements. Those are nice, but only matter if you're already driving your chip at crazy power levels. No, the big win is relieving routing congestion in M1. It is this routing congestion that has throttled the down-scaling of SRAM in recent processes; and the expectation is that by moving to BSPDN (even the initial, simpler, non-nTSV version chosen by TSMC for gen1) SRAM scaling can resume. BUT for that to be of value, you have to be willing to keep the rest of your metal network in place, as low-pitch as before...
In other words, the issue is not "Intel smart, TSMC stupid"; it is priorities.
Intel's priority (for better or worse) it to be able to crank up the *effective* power and frequency of their chips even more. For them, right now, BSPDN matters insofar as it allows for slightly lower power translated into slightly higher clock.
ISMC's priorities are (a) process implementation reliability [hence two stages, BSPDN first, nTSV second a year later] and (b) denser SRAM (which they get some of, even at the first stage of BSPDN without nTSV).
IMHO the longer-term imec/TSMC strategy will also move clocks down to the backside. This will have little effect on power, but it will relieve routing even more, allowing for even denser SRAM. I have no idea, but I would not be surprised if at least part of the slow cautious TSMC strategy is to put together a process that naturally extends to moving the clocking layers to the backside, whereas the faster Intel strategy has been to ignore this and hope that, somehow, it can be retrofitted in the future...
DannyH246 - Tuesday, June 6, 2023 - link
Excellent post! Quite honestly this kind of balanced comparison of the various tech out there is what we would want in the main article. It’s a shame www.IntelTech.com hasn’t done this for a while now.drajitshnew - Wednesday, June 7, 2023 - link
@name99 impressive post.I had been confused for some time about the limitation on scaling of SRAM as traditional 6T SRAM has only transisters which are scaling. Even DRAM with Capacitors is now scaling in production to 12 nm
Quantum Mechanix - Thursday, June 8, 2023 - link
Love your explanation on what's hindering SRAM scaling, not that easy to find out there- bravo!my_wing - Sunday, June 11, 2023 - link
At first it seem like what you talking about IMEC make a bit of sense. But the longer I read from other website and other things (of course a lot still not understand). But what I can conclude is now the following.In July 2021, intel already mentioned a lot about PowerVIA, it that meant that your IMEC paper is in the same class, then TSMC is not behind. Sorry I don't get it.
Intel give us number and it also give us number of Intel 4 without PowerVIA, So now we can even draw some number out from TSMC N3 vs TSMC N5 vs Intel 4.
So the Contacted Gate Pitch is 45nm Vs 51nm Vs 50nm (lower is better).
We know that there is only Single Digit Density improvement TSMC N3E Vs TSMC N5, we know that Intel 4 is at least better then TSMC N5, we know that Intel 4 Vs Intel 4 (with PowerVIA) bring double Digit Density with 6% free frequency boost through less noise and direct connect.
i.e. Intel 4 with PowerVIA beat both TSMC N3E and TSMC N5.
After I saw this from you, I am very worry about TSMC. Because I don't know whether TSMC N2 Vs TSMC N3E will bring single digit density boost (from another Anand Article), if you look at TSMC N2 Vs Intel 4 (with PowerVIA) then you can have the same density profile, that is very bad because we will not see TSMC N2 in another 2 years (2025). I didn't see any Risk Production on TSMC N2 Today, but Intel 4 (with PowerVIA) is at Risk Production stages.
On top you mentioned small steps, i.e. the First Backside Power Delivery might not even use nTSV and Intel PowerVIA meant that is TSMC 2nd Generation Backside Power Delivery.
In my point of view, I felt like that TSMC have all the resource (even more then Intel), they did not do a de-risk and produce a N3(Backside Power Delivery) (they have some many N3 Node name already (N3B/E/P/X) is is clear they can do a N3 (Backside Power Delivery Node), that is very bad for TSMC.
If Intel pull this off and just leave GAA just rename this Intel 4 PowerVia as Intel 20A, then they already fully catch up with TSMC. This is the fact.
What TSMC is doing sound like a company in trouble.
1) Quickly talk to their customer (probably with some price cut) and sell what it can - from what nVidia say they will use TSMC still.
2) Having buzz word and tell people they start procurement and process to start something that is remotely truth. (TSMC say that they start risk production of N2 but the road map show it is H2 2025 like 2 years away and for semi industry this is long for procurement purposes).
3) Having the CEO/CFO saying to analyst that the recent profit dip is temporary and having a good long term (financial tricks) (just like Bob Swam @ Intel), and not the CTO saying we have this tech and that tech so we are good.
4) No admitting this danger and just quick dive into the technology, i.e. have a N3 with backside power delivery, and not just focus on GAA, this is a mistake. The Intel slide show that it is cheap to manufacture Intel 4 with PowerVIA (2nd slides).
5) Your competitor is show you with hard numbers (Contacted Poly Pitch is very hard number and 95% density, people can scan your chip after it is available (meteor lake is 2H 2023), there is little room to cheat, and what you give in >1.15X over TSMC N3E (another article in Anand), so what is ">" meant about/around/best case????.
In other word it is an issue of Intel being smart and TSMC is stupid. This is a Trillion Dollar Company and this is what is happen after Chang left, I am very worry, just like when Paul Otellini and Pat left Intel (I really don't think Larrabee is a failure).
Zoolook - Monday, June 12, 2023 - link
You seem to have missed that Intel is not introducing PowerVia until with 20A and thats half a year before TSMC N2, and looking back at the execution of process improvements the last 10 years between the two companies, Intel will likely still be behind, maybe a bit less but personally I doubt it.my_wing - Wednesday, June 14, 2023 - link
That is the Pre Chang TSMC, post Chang TSMC missed N3B for at least 1 year, no one except Apple is going to use N3B, and the amount of EUV exposure in N3B is way too much, so they reduced in N3E (technically without any SRAM scaling vs N5, then N3E is just a name?). Looking at the post Chang record, I can also assume that TSMC N2P is only going to come out at 202X with delays on the card. CEO is long term planning guy, it was also not day 1 when Paul Otellini left and Intel shows the sinking, it take 3 years for us to know, CEO influence often shown 3+ years and guess what Chang retired 2018, and N3B problem is in 2022 (3/4 yearish).Intel is already ahead (intel 4 is already 100% of what TSMC N3E High Performance is (3 Fins), the density side then intel did not show us or have High Density Library (2 Fins)), not behind you can be a cheerleader for TSMC, I was a TSMC shareholder and I sold that at 117 USD ADR and switch to ASML. With this intel slide, I am starting to switch from ASML to Applied Materials. I put real money to things that I talk, not a fanboy.
You can doubt it but the number 45nm Vs 51nm Vs 50nm, as far as I can see (because they all (all article from different source) say TSMC N3E will not bring density improvement over N5), might be this is not clear enough, it meant in the high performance library, TSMC N3E (next year) = Intel 4.
Intel is already 1 year ahead. As TSMC N3B is not a production ready node. Apple is consider go to N3E for iPhone 16. TSMC N3B with it's high number EUV layer + min density improve just not worth the cost. While Intel 4 with Applied Material help seem to crack to code, and their improve Intel 3 is next year, then that is second generation vs a first real N3 Class from TSMC.
tipoo - Monday, June 5, 2023 - link
Intel will see a monster turnaround through 2025-26. Only fear priced in right now.evilpaul666 - Monday, June 5, 2023 - link
They'll buy back more of their shares to pump the price a bit. Should have plenty of cash since they're getting that CHIPS Act money to pay for manufacturing upgrades.brakdoo - Monday, June 5, 2023 - link
Thermals are a mess. 30% of core area for thermal stuff? What's the benefit of backside power then (just 6% frequency?)? How is their "normalized" power and temperature compared to the regular Intel 4 chip? What was the size of the non backside Intel 4 chip?At >> 10mm2 for 4 E-Core these E-cores are much bigger than regular E-Cores on Meteor Lake (we've seen die shot leaks)
Zero information... Please be more critical and ask these questions when you have the opportunity to directly talk to them instead of just posting their stuff.
BTW: They should've used P-cores instead of E-cores when it comes to thermals.
jjjag - Monday, June 5, 2023 - link
Like anybody from AT will attend VLSI Symposium and be able to ask meaningful questions...VLSI Symposium is focusing on backside power/PowerVia this year, as every major foundry is offering it at the 2nm node (along with ribbon/GAA FET and some other advanced packaging techniques). Intel is going to present some details on their implementation. The focus is the improvement of power via alone, not how big the e-cores are compared to meteor lake.
You are missing the point of the article, the paper, and the content of VLSI Symposium this year. Go look at the program, then once the conference is done in a couple weeks go read the papers.
Ryan Smith - Monday, June 5, 2023 - link
To be sure, we did have a chance to ask questions last week. But those ended up mostly centered around likes like the carrier wafer and wafer slimming, the E-cores, the defect rate, and EDA tools. There are always more questions than there is time to get them answered, at least initially.vlsi_dude - Sunday, July 23, 2023 - link
The 30% of core area for thermals was to to insert redundant thermal monitors (+ trying several thermal monitoring techniques to find which performs better) and also to try out several special thermal mitigation techniques. One can only afford to do this on a test chip and the learnings will be incorporated in the products. The comment about 30% was to convey the point that the design team took the thermal seriously and spent "much area" on getting high quality and irrefutable thermal data and to also study the thermal sensitivitiesIII-V - Monday, June 5, 2023 - link
Wow, 6% higher clock speeds is pretty nice in this day and age. Wonder what the Intel 4 process delivers vs Intel 7 (if anything at all)TristanSDX - Monday, June 5, 2023 - link
For users+ 6% higher clock, 12% higher density
- harder to cool, may throttle decresaing clocks gain
For Intel
+ lower cost for M0
- complex debug (higher cost for next gen cores design), more layers (additional cost despite easy to make), more silicon for carrier, additional costs for thinning and other processing
Overall not so beneficial, TSMC and Sansung have right not to rush with it until it is really needed.
thestryker - Monday, June 5, 2023 - link
The article states that Intel worked around the thermal issue with their design so harder to cool not so much. The shift in pitch is mostly about offsetting the additional costs so this also isn't so much a thing. If the pitch shift alone allows for them to drop one layer of multipatterning it has more than paid for itself.my_wing - Tuesday, June 6, 2023 - link
Lower cost for M0, that is a big plus, this is where you needed EUV (Multiple patterning), the article is actually suggest is M1 layer having benefit.Harder to cool? I think the backside power is mainly copper wires, and copper conduct heat well, look at your heat sink. Yes it can make it worst but I think the situation is not as bad as you guess.
complex debug? More Layers ??? negative for Intel not necessary, even if there are more layers if each layer become simpler then is actually easier to debug. You have power and signal cable tango each other. The layer is more simple.
TSMC and Samsung can say wherever they like but it can meant that TSMC and Samsung underestimate the technology.
ikjadoon - Monday, June 5, 2023 - link
If Intel can deliver on its promises, the company is expecting to be at least two years ahead of TSMC and Samsung in deploying backside power delivery – and that means at least two years of reaping the cost and performance benefits of the technology.//
But that's only ahead of Intel's own nodes, whose performance isn't being detailed quite yet. Intel should pit their Intel 4 / Intel 3 / Intel PDN libraries onto an industry-standard core and even compare it to data for those same industry-standard cores at other fabs.
That's how you'd sell IDM 2.0 to investors & tech media (the only people that don't know this data already, but hold significant power over Intel's future).
trivik12 - Monday, June 5, 2023 - link
Why dont Intel make intel 3 with Power Via. That should help GNR and SRF significantly.dullard - Monday, June 5, 2023 - link
Intel 3 production will be ready to begin mass production ramping soon. Power Via isn't supposed to be ready until 2024. Intel burned themselves badly in the past by putting too many new things into one basket and couldn't deliver. I can see why they waited another generation.Ryan Smith - Monday, June 5, 2023 - link
The process node used here (Intel 4 + PowerVia) is only for R&D purposes. It is not a production node. PowerVia won't go into production until Intel 20A.Using Intel 3 as your base for the test node would have just made things take longer. Intel 3's advancements aren't pertinent to the development of BS-PDN.
(And if you're asking why Intel didn't make an Intel 3 + PowerVia production node, I point back to the fact that PowerVia won't be ready any earlier than in time for Intel 20A)
James5mith - Tuesday, June 6, 2023 - link
Not to skip too far ahead, but how will this impact GPU manufacturing?Modern GPUs are already pushing thermal boundaries with 400-700w power draw. Having to extract that heat through additional layers of silicon seems very very challenging for those higher power/heat situations.
my_wing - Tuesday, June 6, 2023 - link
Because PowerVIA is a more efficient way to power the transistor (6% mentioned), you pump less amps into the transistor and will create less heat.That clean power delivery, in turn, improves the compute performance and the energy efficiency of the chip. Besides the direct efficiency gains from losing less energy to resistance, constructing an E-core with PowerVia technology improved the maximum frequency (fMax) of the core by 6%. Intel doesn’t offer a more detailed explanation as to why this improved their clockspeeds, but I suspect it has to do with a higher voltage actually reaching the transistors themselves, allowing them to clock a bit higher. So you create 6% less heat in the first place, although we don't know how heat will leave the chip. We also don't know the structure of the dummy waffle, since before PowerVIA, the chip is package upside down and PowerVIA is the other way around, with the supportive dummy waffle on top. As heat goes up in physics, the structure/shape of the dummy waffle can be the difference to how heat is leaving the chip itself, are there holes in the dummy waffle, what is the shape of the holes, are those shape in anyway to help the heat leaving the chip, is the dummy waffle have a more heat conductive layer on top will that help the heat leaving the chip.
As Chip is moving from 2D to 2.5D/3D the mentioned joke about there are so little silicone left meaning that there are so many space(air) in between and where these spaces are will impact the heat leaving the chip.
From the article it read a follow:
And while a 6% clockspeed uplift isn’t a massive gain, it’s essentially a “free” improvement coming from a technology that is designed to improve the manufacturability of a chip. Intel has worked harder to get smaller clockspeed improvements in the past.
dwbogardus - Thursday, June 8, 2023 - link
Lower resistance isn't the only benefit of shorter, stouter, more direct power and ground connections provided by BS-PDN. Not mentioned, but every bit as significant, is lower inductance in the power paths. "Ground bounce" in signal return paths from excessive inductance can degrade signal switching margins, and thus frequency and performance. BS-PDN should help.hix - Tuesday, June 6, 2023 - link
well all these gizmos and we are the best charts ,, innovative projects ,, on end we get hot chip that cant go head to head with zen ,and that need 6ghz 300w just to sit nearsame time pay different sites to bash amd epic which halt on 1000days reset and go again ,same time xeons die after 300-500h uptime just wow ,,,on end intel must have super pro chart guys
same time ic designers/fab guys are meh
m53 - Thursday, June 8, 2023 - link
Looks like Intel is really gaining back their process lead vs TSMC in late 2024 timeframe. It's fascinating to see how many people doubted them even though they have the process lead for the longest time in history before they fumbled at 10nm. TSMC also fumbled many times before specially during the introduction of finfet. But they got back into competition over time and even took the lead. So, Intel taking back the lead is not really surprising specially at a time where TSMC is struggling with 3nm yield and delaying the introduction of backside PDN.hix - Friday, June 9, 2023 - link
ppl say same from 2010 , intel fabs suxZoolook - Monday, June 12, 2023 - link
Samsung has been struggling with 3GAE (reported yields at 10-20%), TSMCs N3 started at similar levels as N5 at >70%, now over 80%, I think you mixed up the two companies and their processes.TSMC stated from the start that first N2 would only introduce GAA in 2025 and later versions would get BSPD, when did they delay it?
Before Intel can get into the lead they need to catch up, they haven't shown that they can execute on that yet, but time will tell, it would be good if they can though as it seems Samsung continues to struggle to compete and it would be beneficial to have two competing foundries at the same level.
buxe2quec - Friday, June 16, 2023 - link
I haven't read all comments, maybe someone pointed it out already, but this tech is interesting also because, by having a very thin substrate after the polishing, they could in theory stack multiple dies on top of each other, so that no only wiring will be 3D (as it has been for decades) but also transistors, allowing closer proximity of related functionalities.It is done with memory on top of the die (AMD I don't remember the name), but stacking processing could also be interesting.
Of course, for 2 layers the power wiring would end up on the outer sides, and in any case the chip may need cooling from both sides, so it could end up not as a pizza on top of the motherboard, but as a toaster with instead of heating from both sides of the bread, cooling from both sides.
obed51815 - Thursday, July 20, 2023 - link
Thanks for sharing this post! It's fascinating to see Intel's ambitious plans with PowerVia chip fabrication technology and RibbonFET for gate-all-around transistors. Considering the importance of these technologies in regaining their fab leadership position, Intel's R&D efforts must be at an all-time high. With the stakes so high, their progress in these areas becomes crucial not only for the company but for the entire industry.The upcoming VLSI Symposium is undoubtedly going to be a significant event, drawing attention both inside and outside the company. As Intel moves closer to the production phase, presenting their findings on producing a complex logic test chip becomes a crucial milestone. This evidence of progress will be reassuring to investors and other outsiders, showing that Intel's efforts to get back on track are bearing fruit.
It's impressive to witness the culmination of years of hard work and research, which will eventually bring the "angstrom" era fab nodes into high volume manufacturing next year. Embracing these new technologies could propel Intel forward and potentially position them ahead of the competition, as they venture into the contract chip manufacturing business.
In conclusion, Intel's advancements in chip manufacturing technology are vital for the future of the company and the industry as a whole. We eagerly await the outcomes of the upcoming symposium and wish Intel the best in their journey towards technological excellence.