According to TSMC slides, N7+ vs. N7 can also provide +10% performance at iso-power. So we could see clock speed increases vs. N7. Using a balanced frequency vs. power increase, even a 6% increase in clock speeds could make a next gen Ryzen 4950x reach 5GHz boost while using the same or lower power than a Ryzen 3950x.
Clock speed is the last and final hurdle for AMD to conquer with Zen. I hope the next generation will allow for 5 GHz turbo frequencies on a few cores, to acellerate single-threaded applications even more so than Intel's many Lakes can right now. Allowing the chips to reach high frequencies for lightly threaded tasks doesn't mean it won't consume less power for heavily threaded ones.
Also let's not forget TSMC's 7nm process is creating AMD chiplets with only 1 or 2 cores that can hit those boost clocks. I expect EUV is going to help with the consistency of good cores so hopefully in the lower core counts we will see higher base clocks as well as boost clocks.
I'd have thought they'll push the frequencies again to have a higher base and higher single-core. After all, this provides the most advertised performance. Kinda sucks for overclocking, but you get a good value for what you pay for to start with.
Given the size of Apple's recent SoCs I would be quite shocked if they didn't go for the hightest-end process possible at all times. Which I believe is also what they've done previously.
AFAIK, TSMC has the new nodes N7P, N7+, N6 and N5 that are ready in that order. Apple uses N7P for A13. AMD uses N7+ for Zen 3 (4th gen Ryzen). N6 is evolution of N7P. N7+ is better than N6, and N5 trumps both.
One thing for sure AMD can lower their price even more with these 7nm euv. I believe up to 5ghz is possible. It million questions on how much zen architecture can improve from here and Lisa Su already mention there are more IPC to squeeze.
"One thing for sure AMD can lower their price even more with these 7nm euv"
Every process since 28nm has been cost/transistor go up, not down. This trend is not going to reverse any time soon. Moving to a newer process and 'die shrinking' no longer nets you a cost improvement, and has not for quite some time now.
When TSMC say 2nd Generation 7nm, they are referring to N7P, which is an improved version of N7 based on DUV.
The N7+, is based on EUV, and the next step , 2nd generation of that is N6. With additional layers using EUV.
I have yet to see any concrete answer as to Apple using EUV, and since Apple likely to follow TSMC's terminology, 2nd Generation 7nm likely refers to N7P. Which means Apple hasn't adopted EUV yet.
I was replying to you about the process node and the fact you thought Anton was wrong. Anton was not wrong is what i'm saying. As far as Apple I have no idea but I highly suspect they are on 7nm not the 7nm+ process.
The 5nm node is going to be the next real full node change. This is where the magic begins in my opinion. Once we get most features at 5nm we are taking transistor densities that can have CPU and GPU's all in one chip or chiplets on the same package with very little sacrifices. I suspect the dedicated GPU market to retract a ton once we have proper 5nm APU's.
Looking forward to that too as GPUs at the 7nm process are already full fledged and pack very interesting features not found on high power envelope parts:
Memory bandwidth will have to go up from the roughly ~30 GB/s on 2x 32bit channels found today on most high end SoCs to support that additional compute at 5nm. There is a rumored move to LPDDR5 shortly and there have been 2x 64bit channel configurations such as on the Snapdragon 805 in the past which will help, and the much higher densities of this process will also allow for much larger caches on die to hide low DRAM bandwidth and latencies better.
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
27 Comments
Back to Article
sgeocla - Tuesday, October 8, 2019 - link
According to TSMC slides, N7+ vs. N7 can also provide +10% performance at iso-power.So we could see clock speed increases vs. N7. Using a balanced frequency vs. power increase, even a 6% increase in clock speeds could make a next gen Ryzen 4950x reach 5GHz boost while using the same or lower power than a Ryzen 3950x.
patel21 - Tuesday, October 8, 2019 - link
improving IPC and keeping the same frequency while reducing power will be even more awesome.AshlayW - Tuesday, October 8, 2019 - link
Clock speed is the last and final hurdle for AMD to conquer with Zen. I hope the next generation will allow for 5 GHz turbo frequencies on a few cores, to acellerate single-threaded applications even more so than Intel's many Lakes can right now. Allowing the chips to reach high frequencies for lightly threaded tasks doesn't mean it won't consume less power for heavily threaded ones.FreckledTrout - Tuesday, October 8, 2019 - link
Yes but TSMC can not help with IPC. This is why nobody is mentioning it in regards to the process.Alistair - Tuesday, October 8, 2019 - link
It can improve IPC in the sense that you get more transistors per area.FreckledTrout - Wednesday, October 9, 2019 - link
Yeah sure but doesn't help IPC unless AMD does a new design for said process.FreckledTrout - Tuesday, October 8, 2019 - link
Also let's not forget TSMC's 7nm process is creating AMD chiplets with only 1 or 2 cores that can hit those boost clocks. I expect EUV is going to help with the consistency of good cores so hopefully in the lower core counts we will see higher base clocks as well as boost clocks.GreenReaper - Tuesday, October 8, 2019 - link
I'd have thought they'll push the frequencies again to have a higher base and higher single-core. After all, this provides the most advertised performance. Kinda sucks for overclocking, but you get a good value for what you pay for to start with.dudedud - Tuesday, October 8, 2019 - link
"Two known customers of N7+ are Huawei's Hisilicon with the Kirin 990 5G, and Apple’s A13."Is now confirmed that the A13 is indeed on 7+?
Valantar - Wednesday, October 9, 2019 - link
Given the size of Apple's recent SoCs I would be quite shocked if they didn't go for the hightest-end process possible at all times. Which I believe is also what they've done previously.Rudde - Thursday, October 10, 2019 - link
AFAIK, TSMC has the new nodes N7P, N7+, N6 and N5 that are ready in that order. Apple uses N7P for A13. AMD uses N7+ for Zen 3 (4th gen Ryzen). N6 is evolution of N7P. N7+ is better than N6, and N5 trumps both.Krayzieka - Tuesday, October 8, 2019 - link
One thing for sure AMD can lower their price even more with these 7nm euv. I believe up to 5ghz is possible. It million questions on how much zen architecture can improve from here and Lisa Su already mention there are more IPC to squeeze.edzieba - Wednesday, October 9, 2019 - link
"One thing for sure AMD can lower their price even more with these 7nm euv"Every process since 28nm has been cost/transistor go up, not down. This trend is not going to reverse any time soon. Moving to a newer process and 'die shrinking' no longer nets you a cost improvement, and has not for quite some time now.
p1esk - Wednesday, October 9, 2019 - link
EULksec - Tuesday, October 8, 2019 - link
Wait a min. Anton I think this could be wrong.When TSMC say 2nd Generation 7nm, they are referring to N7P, which is an improved version of N7 based on DUV.
The N7+, is based on EUV, and the next step , 2nd generation of that is N6. With additional layers using EUV.
I have yet to see any concrete answer as to Apple using EUV, and since Apple likely to follow TSMC's terminology, 2nd Generation 7nm likely refers to N7P. Which means Apple hasn't adopted EUV yet.
Frenetic Pony - Tuesday, October 8, 2019 - link
Well, no, 6nm is a separate upgrade path from 7nm+. I'm unsure what Apple is using though, did hear they balked at 7nm+.ksec - Wednesday, October 9, 2019 - link
What do you mean by Separate upgrade path.levizx - Thursday, October 10, 2019 - link
Apple is NOT using EUV. And N6 is a more compatible version of N7+.FreckledTrout - Wednesday, October 9, 2019 - link
TSMC publicly announced they are in high volume production of N7+ aka 7nm+.This is easily searchable, https://www.tsmc.com/tsmcdotcom/PRListingNewsActio...
ksec - Wednesday, October 9, 2019 - link
And that by no means N7+ is being used by Apple. Huawei is also N7+.FreckledTrout - Thursday, October 10, 2019 - link
I was replying to you about the process node and the fact you thought Anton was wrong. Anton was not wrong is what i'm saying. As far as Apple I have no idea but I highly suspect they are on 7nm not the 7nm+ process.melgross - Wednesday, October 9, 2019 - link
Apparently, Apple chose the N7 Pro second generation process instead. Both have their advantages.Anymoore - Tuesday, October 8, 2019 - link
I have to wonder if 7nm+ uses this: https://patents.google.com/patent/US9091930B2/enThey have continued the application at USPTO as well.
It would increase the die size as was seen with Huawei Kirin 990 5G.
Oberoth - Wednesday, October 9, 2019 - link
Is TSMC's 6nm sometimes referred to as 5nm because what was all this news about?https://www.techpowerup.com/259536/tsmc-to-begin-m...
levizx - Thursday, October 10, 2019 - link
No. 5nm already entered risk production months ago.FreckledTrout - Thursday, October 10, 2019 - link
The 5nm node is going to be the next real full node change. This is where the magic begins in my opinion. Once we get most features at 5nm we are taking transistor densities that can have CPU and GPU's all in one chip or chiplets on the same package with very little sacrifices. I suspect the dedicated GPU market to retract a ton once we have proper 5nm APU's.Raqia - Thursday, October 10, 2019 - link
Looking forward to that too as GPUs at the 7nm process are already full fledged and pack very interesting features not found on high power envelope parts:https://www.highperformancegraphics.org/wp-content...
Memory bandwidth will have to go up from the roughly ~30 GB/s on 2x 32bit channels found today on most high end SoCs to support that additional compute at 5nm. There is a rumored move to LPDDR5 shortly and there have been 2x 64bit channel configurations such as on the Snapdragon 805 in the past which will help, and the much higher densities of this process will also allow for much larger caches on die to hide low DRAM bandwidth and latencies better.