I mean, once you get to Cortex-M7 the lines start to blur between an applications processor and a microcontroller, to the point that NXP has started marketing a hybrid SoC called i.MX RT.
High-end microcontrollers have become very fast indeed, with superscalar execution, caches, floating point and soon even SIMD, however a microcontroller doesn't have an MMU and can't run full Linux, so there is still a clear distinction. If you did manage to run a serious benchmark on a microcontroller (say SPEC), it would perform abysmally since it just isn't designed for that.
PIC32 MCUs do have an MMU and some of the higher end models have 32MB ram embedded, or up to 128MB ddr2 externally. They are definitely still microcontrollers though.
Performance is indeed very promising, more than enough for IoT and embedded. The real question would be how much gate's it is in its base layout. If it beats ARM it will skyrocket.
You can probably interpolate performance based on the A15 benchmark shown to reasonable accuracy, but since this isn't a performance SoC. This will likely be used in low-performance applications from Arduino to smart home devices. However, it's relatively high performance for a supplemental controller if we are to believe WD's cherry picked benchmark score :P
I'm a little puzzled why the Xeon E5 (Sandy) has a higher score than the Xeon E5 (Ivy).
I see that the unit they are using is normalized for clock speed (score/MHz) but unless the test is multithreaded and the Sandy had more cores than the Ivy, the IVB core should have higher IPC...
The Sandy Bridge number is the CoreMark certified result, presumably from Intel themselves, whereas Ivy Bridge was benchmarked by the researchers themselves. That probably explains the difference.
There is a long history from the MIPS days to make bogus benchmark comparisons. For example MIPS used to add a pass in GCC which improves Coremark by ~30%. They then quote numbers for MIPS with the pass enabled and for their competitors with the pass disabled eventhough the pass worked equally well for them. That pass is on by default in GCC nowadays, however the trick now is to use an old GCC version for the competition...
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spaceship9876 - Friday, February 15, 2019 - link
I would like to see the performance of this compared to cortex a53 and a55.Wilco1 - Friday, February 15, 2019 - link
This is a simple microcontroller, not a Cortex-A53 equivalent. It's similar to a Cortex-M7 and that gets over 5 Coremarks/MHz.kfishy - Friday, February 15, 2019 - link
I mean, once you get to Cortex-M7 the lines start to blur between an applications processor and a microcontroller, to the point that NXP has started marketing a hybrid SoC called i.MX RT.Wilco1 - Friday, February 15, 2019 - link
High-end microcontrollers have become very fast indeed, with superscalar execution, caches, floating point and soon even SIMD, however a microcontroller doesn't have an MMU and can't run full Linux, so there is still a clear distinction. If you did manage to run a serious benchmark on a microcontroller (say SPEC), it would perform abysmally since it just isn't designed for that.cb88 - Thursday, March 21, 2019 - link
PIC32 MCUs do have an MMU and some of the higher end models have 32MB ram embedded, or up to 128MB ddr2 externally. They are definitely still microcontrollers though.zvonimir - Friday, February 15, 2019 - link
Paper is coming out soon. It is 5 CM/Mhz and about 3 Dhrystone MIPS/MHz. Once it is published, I will add it to GitHub. -ZvonimirZolaIII - Friday, February 15, 2019 - link
Performance is indeed very promising, more than enough for IoT and embedded. The real question would be how much gate's it is in its base layout. If it beats ARM it will skyrocket.Samus - Friday, February 15, 2019 - link
You can probably interpolate performance based on the A15 benchmark shown to reasonable accuracy, but since this isn't a performance SoC. This will likely be used in low-performance applications from Arduino to smart home devices. However, it's relatively high performance for a supplemental controller if we are to believe WD's cherry picked benchmark score :PSantoval - Friday, February 15, 2019 - link
As Wilco mentioned this core is equivalent to the "M" series of ARM cores, not their "A" series. The M series are microcontrollers, not complete SoCs.MrCommunistGen - Friday, February 15, 2019 - link
I'm a little puzzled why the Xeon E5 (Sandy) has a higher score than the Xeon E5 (Ivy).I see that the unit they are using is normalized for clock speed (score/MHz) but unless the test is multithreaded and the Sandy had more cores than the Ivy, the IVB core should have higher IPC...
peevee - Friday, February 15, 2019 - link
Bad testing. What do you expect from Berkley these days?kfishy - Friday, February 15, 2019 - link
The Sandy Bridge number is the CoreMark certified result, presumably from Intel themselves, whereas Ivy Bridge was benchmarked by the researchers themselves. That probably explains the difference.kfishy - Friday, February 15, 2019 - link
This is the paper WD got their numbers from. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/...Wilco1 - Friday, February 15, 2019 - link
There is a long history from the MIPS days to make bogus benchmark comparisons. For example MIPS used to add a pass in GCC which improves Coremark by ~30%. They then quote numbers for MIPS with the pass enabled and for their competitors with the pass disabled eventhough the pass worked equally well for them. That pass is on by default in GCC nowadays, however the trick now is to use an old GCC version for the competition...