I just finished my chip for my ASIC class, I'm running some clock optimization passes overnight as well as one final verification test to make sure it actually does what it's supposed to do. If all goes well, I'll post my die size tomorrow afternoon :)

It's synthesized using 0.25-micron libraries, so it shouldn't be *too* big...I hope.

Thanks to my 6AM bedtime last night I'm basically not tired at all right now, maybe I'll stay up and try to optimize the chip a bit...who am I kidding, I'm sick of this thing. Goodnight folks.