This does not solve the problem of skyrocketing prices due to the slowdown in manufacturing processes, complexity and lack of competition in the sector
Nor does it attempt to. That would happen via competition or just a glut of manufacturing capacity. The former is stalled with a potential for resurgence if Samsung's Nintendo deal goes well, and the latter comes down to whether TSMC can pivot in countries outside of Taiwan.
This doesn't address that but the way packaging technology works offers an alternative path to increasing performance. Instead of cramming more transistors into an similar area based upon new manufacturing process nodes, this enables designers to stich multiple pieces of silicon together to get the same amount of transistors for a design over a larger silicon area. There are certainly trade offs, power consumption and packaging yields being the big ones. Cost is a harder one to determine as new nodes have significantly higher costs associated with them but so does this packaging technology.
The real interesting aspect is power consumption and temperatures. Newer nodes are not offering as great of power savings as they used to. Combine that by scaling up designs to use more functional units over more area but at reduced clocks/voltage to normalize performance, the power consumption could be lower with these new packaging technologies. Temperatures would arguably be lower as well as the power draw would be spread across more area. The downside to this approach is that it does cost more due to additional silicon where as higher voltages/clocks are 'free' in that sense (designs due need more complex VRM for power delivery, better heat sink etc.).
"Reticle super carrier interposer" definitely sounds like a sequence of words I've heard in a reeeally low budget sci fi series that didn't know what any of those words meant. Possibly some sort of Canadian-European coproduction where half the cast had learned their lines phonetically.
But seriously, bigger chips is interesting. The industry is sort of divided between "Is there anything else we can throw into the SOC to use up some of our giant transistor budget we don't know what to do with?" and "Throw infinity more low precision floating point units in because our AI/Graphics problems are sufficiently parallelizable that we'd gladly consume 1,000x the area of current chips without blinking." I wonder if the economics really work out for 2x bigger chips today the way they have for most of the history of Moore's law. If you could fab a 2x bigger chip in the 90's, you were obviously going to be instantly buried in customers because everybody knew exactly what they'd do with an extra million transistors and was just waiting for the hardware to get there. Today, "more GPU, but it costs over 2X as much because it's 2X the silicon and the fab process is more complex, and latencies aren't improved - only compute throughput" may not be as much of a slam dunk.
Using UCIe-Advanced based die-to-die connectivity latency is expected to be under 2ns, and pJ/bit better than 40x improved compared to PCIe Gen5.
Putting everything that works together on one chip and what doesn't (or can be split) on seperate chiplets (using silicon made on different nodes) not only is effective use of the area but cost effective from a manufacturing perspective.
2x the cost for 2x the performance isn't a loss, other gains are the power efficiency and the size; both of which are significant for day to day operating costs. A new motherboard with a new chip that can replace a system that took up 3-4x as much space under the same power budget is a huge savings, a slam dunk with a swish.
So reticle limit will be halved in the future but chips can be stitched up to 8X reticle limit so about 4 of todays reticle limit size chips together. Interesting
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Dante Verizon - Tuesday, April 30, 2024 - link
This does not solve the problem of skyrocketing prices due to the slowdown in manufacturing processes, complexity and lack of competition in the sectormukiex - Tuesday, April 30, 2024 - link
Nor does it attempt to. That would happen via competition or just a glut of manufacturing capacity. The former is stalled with a potential for resurgence if Samsung's Nintendo deal goes well, and the latter comes down to whether TSMC can pivot in countries outside of Taiwan.Kevin G - Wednesday, May 1, 2024 - link
This doesn't address that but the way packaging technology works offers an alternative path to increasing performance. Instead of cramming more transistors into an similar area based upon new manufacturing process nodes, this enables designers to stich multiple pieces of silicon together to get the same amount of transistors for a design over a larger silicon area. There are certainly trade offs, power consumption and packaging yields being the big ones. Cost is a harder one to determine as new nodes have significantly higher costs associated with them but so does this packaging technology.The real interesting aspect is power consumption and temperatures. Newer nodes are not offering as great of power savings as they used to. Combine that by scaling up designs to use more functional units over more area but at reduced clocks/voltage to normalize performance, the power consumption could be lower with these new packaging technologies. Temperatures would arguably be lower as well as the power draw would be spread across more area. The downside to this approach is that it does cost more due to additional silicon where as higher voltages/clocks are 'free' in that sense (designs due need more complex VRM for power delivery, better heat sink etc.).
wrosecrans - Tuesday, April 30, 2024 - link
"Reticle super carrier interposer" definitely sounds like a sequence of words I've heard in a reeeally low budget sci fi series that didn't know what any of those words meant. Possibly some sort of Canadian-European coproduction where half the cast had learned their lines phonetically.But seriously, bigger chips is interesting. The industry is sort of divided between "Is there anything else we can throw into the SOC to use up some of our giant transistor budget we don't know what to do with?" and "Throw infinity more low precision floating point units in because our AI/Graphics problems are sufficiently parallelizable that we'd gladly consume 1,000x the area of current chips without blinking." I wonder if the economics really work out for 2x bigger chips today the way they have for most of the history of Moore's law. If you could fab a 2x bigger chip in the 90's, you were obviously going to be instantly buried in customers because everybody knew exactly what they'd do with an extra million transistors and was just waiting for the hardware to get there. Today, "more GPU, but it costs over 2X as much because it's 2X the silicon and the fab process is more complex, and latencies aren't improved - only compute throughput" may not be as much of a slam dunk.
Rοb - Saturday, May 4, 2024 - link
In US-terms it's 'butts in the seats'.Using UCIe-Advanced based die-to-die connectivity latency is expected to be under 2ns, and pJ/bit better than 40x improved compared to PCIe Gen5.
Putting everything that works together on one chip and what doesn't (or can be split) on seperate chiplets (using silicon made on different nodes) not only is effective use of the area but cost effective from a manufacturing perspective.
2x the cost for 2x the performance isn't a loss, other gains are the power efficiency and the size; both of which are significant for day to day operating costs. A new motherboard with a new chip that can replace a system that took up 3-4x as much space under the same power budget is a huge savings, a slam dunk with a swish.
MoogleW - Thursday, May 2, 2024 - link
So reticle limit will be halved in the future but chips can be stitched up to 8X reticle limit so about 4 of todays reticle limit size chips together. Interesting