I knew the older nodes were profitable, but the sheer magnitude is astonishing! It's also interesting to see which processes hang around and become "legacy" and which ones fade away (or almost never really exist like 20 nm, but that wasn't just TSMC).
A lot of microcontrollers, especially ARM, are on ~40 and 90nm nodes. ST Micro's STM32 series, for example. Microchip's fabs (they produce the ATMega lines seen in Arduinos, and a couple of lines of ARM Cortex-M (Adafruit is big on them, for their Arduino-like Feather line) chips, seem to be 250 and 150nm or so, according to Wikipedia.
The margins reported are false. They make big margins, but not that big, and the "net revenue" that Cutress reports is just revenue. There is such thing as "net revenue" in financial reporting.
You know very little about financial reporting do you? Net revenue is tied to gross margin. It's reported when your revenue is generated from commissions, ie you don't pay your suppliers unless the item is sold.
It's not very relevant to TSMC, but it is a very real accounting terms. TSMC is reporting Gross Revenue.
80% of revenue is from smartphone and high performance computing. But only 74% of revenue is from below 40nm. So that implies some smartphone and HPC processors are 40nm+. Which seems surprising.
Anything that doesn't need high performance, high volumes, or is size constrained by its IO pins. Older nodes are cheaper to make, cheaper to design, and for really small chips needing enough size to connect your pins means smaller processes eventually mean wasted empty space not more chips/wafer.
N5 is officially a long node. There's N5 now, N5P will start HVM later this year and N4 will follow next year. These process variants will be available for several years.
Building an IC is a combination of costs, and sometimes the older nodes give you the cheapest costs per die. In general, you buy wafers from the fab (the fab doesn't really care what you're putting on the wafer) - on older nodes the wafers are cheaper, on newer nodes they're a lot more expensive. If you get a lot more die per wafer on the newer node, it may be cheaper to use the new process; if you don't, it doesn't make sense. Newer, smaller nodes let you pack on a lot more digital circuitry (or, conversely, let you make your die smaller, and thus cheaper). However, things like analog circuitry don't scale well - an op-amp at 55 nm isn't any smaller than an op-amp at 20 nm. This is also true for I/O pads on the die. Things like CPUs, GPUs, and RAM are great fits for new process nodes - they're digital and they scale well so the astronomical wafer costs are balanced by the astronomical number of additional transistors you can lay down. Analog ICs are really comfortable at ancient technology nodes - 130 and 180 nm have excellent analog characteristics, and newer process nodes don't make the die any smaller but do make them eye-wateringly more expensive. Microcontrollers live in the middle - we built an ASIC 5 years ago that was roughly 50% analog, and 50% digital (200 MHz ARM with RAM/Flash, etc), and it turned out that, at the volume we were producing, 40 nm was the sweet spot with the lowest die cost.
One suggestion for an addition to this informative article is maybe a table showing the lifetime of the different processes. When did they first ship risk production to when they dropped below 1% or some other criteria.
some of TSMC's nodes are intended to be long term support nodes that last for many years, others are short termers intended for companies continually chasing the latest and greatest. Most of the time the short term ones are variants rolled up into one of the larger reporting buckets with at least one long term process as well. 10 didn't have a long term version which is why they quickly faded out. Looking at semi-wiki's longer term chart, it looks like 20 was largely superseded by/rolled into 16, before briefly popping up again as a sliver again when it was split out after being largely retired.
IIRC TSMC's 20nm wasn't a real node shrink, it was basically 28nm with FinFET, it was rather quickly replaced with their 16 nm which was developed for FinFET from the start. It was never a great node, more of a stopgap to try to catch up to Intel at the time.
>>> I'm surprised nobody has stuff manufacturing on TSMC 10nm & 20nm. Probably a combination of reasons. The customers (Intel, AMD, NVidia, etc) who could afford the mask costs for 10/20, and need the performance/logic density, of those nodes are the same customers who can afford the mask costs for 7nm, and need 7 nm performance and logic density. They need it, they can afford it, they move.
Almost everyone else can get by with larger, cheaper nodes. Sure, they COULD transition to 20 nm now that the 20 nm fabs are empty and 20 nm wafers have gotten cheaper, but they'd have to redesign their chip ($20-50M USD or more) and build expensive new masks, and it's likely that the cost savings just aren't there for them.
The IO die was made using 14nm because by nature IO scales poorly with shrinking nodes, I would not expect major gains in eficiency from it going to 7 nm, and there is no point in going to 10nm because AFAIK TSMC transitioned that production capacity to 7 nm. I doubt there exist any iddle equipment just for 10nm.
Neither AMD nor Nvidia used 20 nm, they stayed on 28nm until they moved to 16nm, which led to 28nm being the node that holds the record for most generations of pc graphics in recent years. It was a cludge of a node with relatively small benefits and cost/performance increased compared to staying on 28nm.
TSMC 20nm was a dud with high leakage and minimal scaling over 28nm, so it makes sense for discontinuation. 20nm was TSMC's smallest process using planar transistors; TSMC "16nm" is just rebranded 20nm with FinFETs.
I don't understand the market division. 80% for HPC and smartphones would mean (for example) that 40nm and down are all in these segments. I can believe that there are phone chips being manufactured on older processes, but to this extent?
Something must have happened around 2016 at TMSC, because they were able to to go 16 to 10, 10 to 7, 7 to 5 in 1.5year intervals. Intel needed six years to make transition from 14 to 10. TMSC is moving at 4x the speed of Intel, when it comes to process nodes. Intel would need to improve its process delivery performance by nearly 10x to overtake TMSC in next 10 years.
I think it was TSMC's partnership and nurturing of ASML that paid off. TSMC is ASML's biggest customer. There is some comment on what ASML is doing here (absent the nurturing by TSMC) here https://www.fool.com/investing/2021/04/21/better-s...
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yeeeeman - Thursday, April 15, 2021 - link
Nice!nandnandnand - Thursday, April 15, 2021 - link
7nm should be a great "budget node" by the time 3nm lands (or a year after).shabby - Thursday, April 15, 2021 - link
Intel: *whimpers*nismotigerwvu - Thursday, April 15, 2021 - link
I knew the older nodes were profitable, but the sheer magnitude is astonishing! It's also interesting to see which processes hang around and become "legacy" and which ones fade away (or almost never really exist like 20 nm, but that wasn't just TSMC).dwillmore - Thursday, April 15, 2021 - link
Maybe I should have replied to your comment with my request for a 'process lifetime' table as we're clearly thinking along the same lines.smalM - Thursday, April 15, 2021 - link
https://fuse.wikichip.org/wp-content/uploads/2020/...at_clucks - Tuesday, April 20, 2021 - link
I wonder who are their 110/130nm customers. It's showing impressive cyclic regularity year after year.1_rick - Thursday, April 15, 2021 - link
A lot of microcontrollers, especially ARM, are on ~40 and 90nm nodes. ST Micro's STM32 series, for example. Microchip's fabs (they produce the ATMega lines seen in Arduinos, and a couple of lines of ARM Cortex-M (Adafruit is big on them, for their Arduino-like Feather line) chips, seem to be 250 and 150nm or so, according to Wikipedia.JoeDuarte - Friday, April 16, 2021 - link
The margins reported are false. They make big margins, but not that big, and the "net revenue" that Cutress reports is just revenue. There is such thing as "net revenue" in financial reporting.dotjaz - Sunday, April 18, 2021 - link
You know very little about financial reporting do you? Net revenue is tied to gross margin. It's reported when your revenue is generated from commissions, ie you don't pay your suppliers unless the item is sold.It's not very relevant to TSMC, but it is a very real accounting terms. TSMC is reporting Gross Revenue.
ingwe - Thursday, April 15, 2021 - link
Biting the bullet is doing something that is painful. Biting the dust is what you are looking for. Idioms are a pain.meacupla - Thursday, April 15, 2021 - link
I wonder what still uses those older nodesnandnandnand - Thursday, April 15, 2021 - link
Automotive, analog, display drivers, power management ICs, RF devices, CMOS image sensors, etc.martinpw - Thursday, April 15, 2021 - link
80% of revenue is from smartphone and high performance computing. But only 74% of revenue is from below 40nm. So that implies some smartphone and HPC processors are 40nm+. Which seems surprising.smalM - Thursday, April 15, 2021 - link
total revenue ≠ revenue from wafer productionDanNeely - Thursday, April 15, 2021 - link
Anything that doesn't need high performance, high volumes, or is size constrained by its IO pins. Older nodes are cheaper to make, cheaper to design, and for really small chips needing enough size to connect your pins means smaller processes eventually mean wasted empty space not more chips/wafer.Linustechtips12#6900xt - Thursday, April 15, 2021 - link
it honestly makes me wonder if 5nm is gonna get treated like 20 nm like a steping stone to 3nm/ 3nm euvnandnandnand - Thursday, April 15, 2021 - link
Who knows, but I think the more interesting transition will be TSMC moving to GAAFETs at 2nm.FreckledTrout - Monday, April 19, 2021 - link
That's when things get very interesting. The density and power improvements are supposed to be massive.smalM - Thursday, April 15, 2021 - link
N5 is officially a long node. There's N5 now, N5P will start HVM later this year and N4 will follow next year. These process variants will be available for several years.FrankSchwab - Thursday, April 15, 2021 - link
Building an IC is a combination of costs, and sometimes the older nodes give you the cheapest costs per die. In general, you buy wafers from the fab (the fab doesn't really care what you're putting on the wafer) - on older nodes the wafers are cheaper, on newer nodes they're a lot more expensive. If you get a lot more die per wafer on the newer node, it may be cheaper to use the new process; if you don't, it doesn't make sense.Newer, smaller nodes let you pack on a lot more digital circuitry (or, conversely, let you make your die smaller, and thus cheaper). However, things like analog circuitry don't scale well - an op-amp at 55 nm isn't any smaller than an op-amp at 20 nm. This is also true for I/O pads on the die.
Things like CPUs, GPUs, and RAM are great fits for new process nodes - they're digital and they scale well so the astronomical wafer costs are balanced by the astronomical number of additional transistors you can lay down. Analog ICs are really comfortable at ancient technology nodes - 130 and 180 nm have excellent analog characteristics, and newer process nodes don't make the die any smaller but do make them eye-wateringly more expensive. Microcontrollers live in the middle - we built an ASIC 5 years ago that was roughly 50% analog, and 50% digital (200 MHz ARM with RAM/Flash, etc), and it turned out that, at the volume we were producing, 40 nm was the sweet spot with the lowest die cost.
dwillmore - Thursday, April 15, 2021 - link
One suggestion for an addition to this informative article is maybe a table showing the lifetime of the different processes. When did they first ship risk production to when they dropped below 1% or some other criteria.Kamen Rider Blade - Thursday, April 15, 2021 - link
I'm surprised nobody has stuff manufacturing on TSMC 10nm & 20nm.I kind think of plenty of supporting pieces on a MoBo to manufacture on 10nm and 20nm.
DanNeely - Thursday, April 15, 2021 - link
some of TSMC's nodes are intended to be long term support nodes that last for many years, others are short termers intended for companies continually chasing the latest and greatest. Most of the time the short term ones are variants rolled up into one of the larger reporting buckets with at least one long term process as well. 10 didn't have a long term version which is why they quickly faded out. Looking at semi-wiki's longer term chart, it looks like 20 was largely superseded by/rolled into 16, before briefly popping up again as a sliver again when it was split out after being largely retired.Zoolook - Tuesday, April 20, 2021 - link
IIRC TSMC's 20nm wasn't a real node shrink, it was basically 28nm with FinFET, it was rather quickly replaced with their 16 nm which was developed for FinFET from the start. It was never a great node, more of a stopgap to try to catch up to Intel at the time.FrankSchwab - Thursday, April 15, 2021 - link
>>> I'm surprised nobody has stuff manufacturing on TSMC 10nm & 20nm.Probably a combination of reasons.
The customers (Intel, AMD, NVidia, etc) who could afford the mask costs for 10/20, and need the performance/logic density, of those nodes are the same customers who can afford the mask costs for 7nm, and need 7 nm performance and logic density. They need it, they can afford it, they move.
Almost everyone else can get by with larger, cheaper nodes. Sure, they COULD transition to 20 nm now that the 20 nm fabs are empty and 20 nm wafers have gotten cheaper, but they'd have to redesign their chip ($20-50M USD or more) and build expensive new masks, and it's likely that the cost savings just aren't there for them.
Kamen Rider Blade - Thursday, April 15, 2021 - link
I'm thinking pieces like AMD's Chipset can be made on 20nm & 10nm.https://en.wikipedia.org/wiki/List_of_AMD_chipsets...
-> 300/400 series chipsets are made using 55 nm
-> The X570 chipset is a repurposed Matisse IO die made using the 14 nm Global Foundries process
Imagine if AM5's next generation Chipsets were made on 20nm / 10nm.
The budget one can go on 20nm while the Top Tier Chipset can go to 10nm.
That would be a tremendous improvement in terms of Power Efficiency/Transistor Density/PCIe Lanes you can slap in to AM5
valinor89 - Friday, April 16, 2021 - link
The IO die was made using 14nm because by nature IO scales poorly with shrinking nodes, I would not expect major gains in eficiency from it going to 7 nm, and there is no point in going to 10nm because AFAIK TSMC transitioned that production capacity to 7 nm. I doubt there exist any iddle equipment just for 10nm.nandnandnand - Friday, April 16, 2021 - link
Rumor is that Zen 4 desktop will have a 6nm I/O die.It doesn't scale as well, but it is better.
FreckledTrout - Monday, April 19, 2021 - link
It would be beneficial in very lower power devices to shave some IO die power usage off.Zoolook - Tuesday, April 20, 2021 - link
Neither AMD nor Nvidia used 20 nm, they stayed on 28nm until they moved to 16nm, which led to 28nm being the node that holds the record for most generations of pc graphics in recent years. It was a cludge of a node with relatively small benefits and cost/performance increased compared to staying on 28nm.The Von Matrices - Friday, April 16, 2021 - link
TSMC 20nm was a dud with high leakage and minimal scaling over 28nm, so it makes sense for discontinuation. 20nm was TSMC's smallest process using planar transistors; TSMC "16nm" is just rebranded 20nm with FinFETs.TristanSDX - Friday, April 16, 2021 - link
shares at revenue, says nothing as price of wafer vary depending on processhanselltc - Monday, April 19, 2021 - link
Why is 10 so dead lolRSAUser - Tuesday, April 20, 2021 - link
Because it was finfet, those tools and fabs were repurposed for 7nm.hanselltc - Tuesday, April 20, 2021 - link
I seeZoolook - Tuesday, April 20, 2021 - link
I'd wish Anandtech would use the proper descriptions of wafer tech, the so called 12-inch wafers are actually 300mm or 11.8 inches.ET - Tuesday, April 20, 2021 - link
I don't understand the market division. 80% for HPC and smartphones would mean (for example) that 40nm and down are all in these segments. I can believe that there are phone chips being manufactured on older processes, but to this extent?Atom2 - Tuesday, April 27, 2021 - link
Something must have happened around 2016 at TMSC, because they were able to to go 16 to 10, 10 to 7, 7 to 5 in 1.5year intervals. Intel needed six years to make transition from 14 to 10. TMSC is moving at 4x the speed of Intel, when it comes to process nodes. Intel would need to improve its process delivery performance by nearly 10x to overtake TMSC in next 10 years.Sorcery - Wednesday, April 28, 2021 - link
I think it was TSMC's partnership and nurturing of ASML that paid off. TSMC is ASML's biggest customer. There is some comment on what ASML is doing here (absent the nurturing by TSMC) here https://www.fool.com/investing/2021/04/21/better-s...