Incredible. I didn't believe it when I first saw an article about this. Because cross-die connectivity, which I know was something nVidia paid a lot for a larger overall individual die. But the full explanation makes sense. This is truly game-changing. I wonder about the clock rate. Is this 1+Ghz, or sub-200 Mhz?
You should have asked how this approach holds up against Panel-Level Packaging (PLP).
Interconnect between chips would be slightly slower but all chips were 100% working, max possible size much bigger than these ~210x210mm, integration of DRAM/3DXPoint possible and everything would be much cheaper.
Is the faulty core bypass fixed or changeable (ie if a core fails sometime in the future can it be bypassed) ? How are defective inter die links handled ?
Thanks Ian! Amazing chip, but my question is (would have been if there): How fault-tolerant is this design? We all know that as the transistor count goes up, so does the chance of having too many manufacturing defects that render an IC useless. With this enormous number of transistors, the accumulated number of faults must be substantial. I know they addressed fault-tolerance, but only sort-of. Do they have a (even just one) functional chip they can demonstrate? Showing silicon but not silicon in action raises more questions for me than it answers.
I asked a similar question on Quora regarding wafer yields, and an employee of Cerebras answered it thankfully. To quote him:
Manufacturing an entire wafer without an error is impossible, but Cerebras found a way around it. The Cerebras WSE is made of 84 processing tiles, similar to individual chips, and each tile has redundant processor cores, memory, and I/O. When one part of a tile fails, the extra functions are substituted in their place through software tools, making it seem like a fully functioning tile. As a result, the company can theoretically have 100% yield of all tiles on a wafer and all wafers produced
More precisely, it depends on how many customers they have. If they have spent tens of millions on development and only have 10 customers, well they will be paying a lot more than if they have hundreds of customers.
That's quite impressive, though I am not sure if they made this more as a proof of concept than as a viable product. By the way, despite mentioning that the *silicon* is 46,225 mm^2, which assuming the (monster of a) chip is a perfect square indeed corresponds to 21.5 cm x 21.5 cm, the numbers do not quite add up.
A square with 21.5 cm sides has 30.40 (=>21.5 x √2) cm diagonals, which is larger than the size of a 300 mm wafer. Thus there is no way to make a square die with 215 mm sides and reach that die area unless you move up to a 450 mm wafer, which as of right now is on ice. My guess is that the entire chip, along with its package, is a square with 215 mm sides.
Clipping or rounding the corners of the die a little bit would also not result in these area and side numbers. Allowing a headroom of 0.5 cm for each corner to make the fab process more comfortable the die should have at best 20.5 cm sides for 29 cm diagonals and a die area of 42,025 mm^2.
as I know they are not 300mm - it`s 12" ;) EETimes have more details - it seems to be not only a concept: "The whopping 46,225mm2 die consumes 15kW, packs 400,000 cores, and is running in a handful of systems with at least one unnamed customer" really amazing! And yes 450mm (18" hehe) is on ice, but maybe this is in future a turning point for the research...
15 kW? Doesn't that make their claim of being more efficient a bit relative? How many dedicated but smaller deep learning accelerators that already exist can one run on that kind of energy budget? I get the argument that the fastest solution is the one where the information being worked on basically never leaves the chip, but how does this really compare to more conventionally sized solutions?
The pictures above showing the cross die connectivity show that the device is NOT a perfect square. The device has an array of 7 by 12 dies each of which is rectangular not square.
Yes, the small dies are rectangular and form a 7 x 12 pattern but the full die is still a square. Check out the "Cross-die Wires" picture which shows the full die overlaid on the wafer and you'll understand why. It wouldn't make sense to make the entire die rectangular, because they would have wasted even more die space from the wafer.
Cutting a perfect square from a circle wastes less space than cutting any other rectangular shape from it (an octagon would have been much better, but let's not get greedy). In the last picture we see the real die, not a rendering, and it's clear (despite the perspective of the picture playing a little bit of trick) that it's a perfect square.
Depends on how many they sell and how much the R & D cost was. The cost per wafer (around $5000) is probably a small part of the total cost. It will also depend on whether they can sell a cut down version to use up wafers with too many defects. (An individual die could be mounted on a PCIe card in a conventional computer - the full product requires a specially designed system.)
There is actually very little benefit to this approach.
The reason is simple - power consumption. Not mentioned in the article is that the chip takes a whooping 15 KW! You need insane refrigeration to keep something like this working. This is primarily why you don't get more CPU cores per chip - power density.
It's not that these people have leapfrogged Intel or AMD in any way - the approach is simply impractical for the vast majority of applications.
Now are there actual benefits to the close clustering of the chips? Absolutely, the latency between cores is really small. How much does that matter ... well, it greatly depends on the workload.
In case of ML it might very well make sense... bandwidth seems to be the limiting factor in training, which means it needs a lot of bw - which means it eats a lot of power not doing compute but moving data around. This design cuts down on those power costs so it might very well out-perform a 30kw cluster worth of smaller accelerators which all waste loads of power just pumping data around.
Core should be in quotes. Its is basically a shader unit. Still power consumption looks like it is in the ballpark of reasonable. If you go based on "core" count this thing is 78 titan v's. Which works out to 192 watts per titan equivalent. Obviously this is an extreme simplification but it shows how the math can work. 15kw sounds like a lot but if it is replacing dozens of gpus and their host systems it can still come out on top in terms of efficiency.
They are also claiming water cooling is sufficient and I don't see any reason to doubt them on that. Thermal density should be similar to a gpu but an air cooler just isn't going to scale well to something that large. Water shouldn't have that problem.
2 obvious things which should have been done 10 years ago but big companies are too conservative): + in-memory computing + wafer-scale (it is idiotic to cut wafers for datacenters)
- not general-purpose, limited market, high fixed cost proportion.
Just one microcircuit per plate? Incredible. I think this is a step into the future. I admire scientists and inventors. I wonder which university you need to enter and what stages of preparation and education you need to go through in order to become a specialist and invent a deep learning processor. I know a service https://www.sopservices.net/sop-writing-services/ which will help to prepare a personal application for admission, but the further success of the training already depends on each of us. To invent something is incredible success.
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Andy Chow - Monday, August 19, 2019 - link
Incredible. I didn't believe it when I first saw an article about this. Because cross-die connectivity, which I know was something nVidia paid a lot for a larger overall individual die. But the full explanation makes sense. This is truly game-changing. I wonder about the clock rate. Is this 1+Ghz, or sub-200 Mhz?anonymous5 - Monday, August 19, 2019 - link
sub-200 Mhz probably would not even have thermal expansion or water cooling problems. has to be 1GHz+brakdoo - Tuesday, August 20, 2019 - link
You should have asked how this approach holds up against Panel-Level Packaging (PLP).Interconnect between chips would be slightly slower but all chips were 100% working, max possible size much bigger than these ~210x210mm, integration of DRAM/3DXPoint possible and everything would be much cheaper.
Duncan Macdonald - Tuesday, August 20, 2019 - link
Is the faulty core bypass fixed or changeable (ie if a core fails sometime in the future can it be bypassed) ?How are defective inter die links handled ?
Ian Cutress - Friday, August 23, 2019 - link
It looks like there are about 1-1.5% spare cores onboard, and defective cores are bypassed with one of the spare cores being enabled in its place.Achtung_BG - Tuesday, August 20, 2019 - link
46225 mm2 OMG!!! One chip per wafer unbelievable....PixyMisa - Tuesday, August 20, 2019 - link
I anticipate a moderate degree of expense in acquiring this device.PeachNCream - Wednesday, August 21, 2019 - link
And the understatement of the year award goes to PixyMisa!willis936 - Tuesday, August 20, 2019 - link
The Q to A ratio in that Q and A session is quite low.eastcoast_pete - Tuesday, August 20, 2019 - link
Thanks Ian! Amazing chip, but my question is (would have been if there): How fault-tolerant is this design? We all know that as the transistor count goes up, so does the chance of having too many manufacturing defects that render an IC useless. With this enormous number of transistors, the accumulated number of faults must be substantial. I know they addressed fault-tolerance, but only sort-of. Do they have a (even just one) functional chip they can demonstrate? Showing silicon but not silicon in action raises more questions for me than it answers.obama gaming - Thursday, August 22, 2019 - link
I asked a similar question on Quora regarding wafer yields, and an employee of Cerebras answered it thankfully. To quote him:Manufacturing an entire wafer without an error is impossible, but Cerebras found a way around it. The Cerebras WSE is made of 84 processing tiles, similar to individual chips, and each tile has redundant processor cores, memory, and I/O. When one part of a tile fails, the extra functions are substituted in their place through software tools, making it seem like a fully functioning tile. As a result, the company can theoretically have 100% yield of all tiles on a wafer and all wafers produced
drexnx - Tuesday, August 20, 2019 - link
"everything is amortized across the wafer"talk about a non-answer to the question - "depends on the house" is probably a more accurate one
Adam7288 - Tuesday, August 20, 2019 - link
More precisely, it depends on how many customers they have. If they have spent tens of millions on development and only have 10 customers, well they will be paying a lot more than if they have hundreds of customers.Santoval - Tuesday, August 20, 2019 - link
That's quite impressive, though I am not sure if they made this more as a proof of concept than as a viable product. By the way, despite mentioning that the *silicon* is 46,225 mm^2, which assuming the (monster of a) chip is a perfect square indeed corresponds to 21.5 cm x 21.5 cm, the numbers do not quite add up.A square with 21.5 cm sides has 30.40 (=>21.5 x √2) cm diagonals, which is larger than the size of a 300 mm wafer. Thus there is no way to make a square die with 215 mm sides and reach that die area unless you move up to a 450 mm wafer, which as of right now is on ice. My guess is that the entire chip, along with its package, is a square with 215 mm sides.
Clipping or rounding the corners of the die a little bit would also not result in these area and side numbers. Allowing a headroom of 0.5 cm for each corner to make the fab process more comfortable the die should have at best 20.5 cm sides for 29 cm diagonals and a die area of 42,025 mm^2.
peru3232 - Tuesday, August 20, 2019 - link
as I know they are not 300mm - it`s 12" ;)EETimes have more details - it seems to be not only a concept: "The whopping 46,225mm2 die consumes 15kW, packs 400,000 cores, and is running in a handful of systems with at least one unnamed customer"
really amazing!
And yes 450mm (18" hehe) is on ice, but maybe this is in future a turning point for the research...
eastcoast_pete - Wednesday, August 21, 2019 - link
15 kW? Doesn't that make their claim of being more efficient a bit relative? How many dedicated but smaller deep learning accelerators that already exist can one run on that kind of energy budget? I get the argument that the fastest solution is the one where the information being worked on basically never leaves the chip, but how does this really compare to more conventionally sized solutions?Duncan Macdonald - Tuesday, August 20, 2019 - link
The pictures above showing the cross die connectivity show that the device is NOT a perfect square. The device has an array of 7 by 12 dies each of which is rectangular not square.Santoval - Tuesday, August 20, 2019 - link
Yes, the small dies are rectangular and form a 7 x 12 pattern but the full die is still a square. Check out the "Cross-die Wires" picture which shows the full die overlaid on the wafer and you'll understand why. It wouldn't make sense to make the entire die rectangular, because they would have wasted even more die space from the wafer.Cutting a perfect square from a circle wastes less space than cutting any other rectangular shape from it (an octagon would have been much better, but let's not get greedy). In the last picture we see the real die, not a rendering, and it's clear (despite the perspective of the picture playing a little bit of trick) that it's a perfect square.
atearen - Tuesday, August 20, 2019 - link
1 chip per wafer and 18GB of SRAM, how much should they charge to make this financially viable?Duncan Macdonald - Tuesday, August 20, 2019 - link
Depends on how many they sell and how much the R & D cost was. The cost per wafer (around $5000) is probably a small part of the total cost. It will also depend on whether they can sell a cut down version to use up wafers with too many defects. (An individual die could be mounted on a PCIe card in a conventional computer - the full product requires a specially designed system.)Threska - Tuesday, August 20, 2019 - link
Sheriff Brody: You gonna need a bigger heatsink.vladpetric - Thursday, August 22, 2019 - link
There is actually very little benefit to this approach.The reason is simple - power consumption. Not mentioned in the article is that the chip takes a whooping 15 KW! You need insane refrigeration to keep something like this working. This is primarily why you don't get more CPU cores per chip - power density.
It's not that these people have leapfrogged Intel or AMD in any way - the approach is simply impractical for the vast majority of applications.
Now are there actual benefits to the close clustering of the chips? Absolutely, the latency between cores is really small. How much does that matter ... well, it greatly depends on the workload.
jospoortvliet - Saturday, August 24, 2019 - link
In case of ML it might very well make sense... bandwidth seems to be the limiting factor in training, which means it needs a lot of bw - which means it eats a lot of power not doing compute but moving data around. This design cuts down on those power costs so it might very well out-perform a 30kw cluster worth of smaller accelerators which all waste loads of power just pumping data around.twtech - Saturday, August 31, 2019 - link
15KW sounds like a lot, but with 400k cores, it's only 0.0375 watts per core.biohazard918 - Friday, September 6, 2019 - link
Core should be in quotes. Its is basically a shader unit. Still power consumption looks like it is in the ballpark of reasonable. If you go based on "core" count this thing is 78 titan v's. Which works out to 192 watts per titan equivalent. Obviously this is an extreme simplification but it shows how the math can work. 15kw sounds like a lot but if it is replacing dozens of gpus and their host systems it can still come out on top in terms of efficiency.They are also claiming water cooling is sufficient and I don't see any reason to doubt them on that. Thermal density should be similar to a gpu but an air cooler just isn't going to scale well to something that large. Water shouldn't have that problem.
peevee - Thursday, August 29, 2019 - link
2 obvious things which should have been done 10 years ago but big companies are too conservative):+ in-memory computing
+ wafer-scale (it is idiotic to cut wafers for datacenters)
- not general-purpose, limited market, high fixed cost proportion.
Greys - Wednesday, August 26, 2020 - link
Just one microcircuit per plate? Incredible. I think this is a step into the future. I admire scientists and inventors. I wonder which university you need to enter and what stages of preparation and education you need to go through in order to become a specialist and invent a deep learning processor. I know a service https://www.sopservices.net/sop-writing-services/ which will help to prepare a personal application for admission, but the further success of the training already depends on each of us. To invent something is incredible success.WilliamErups - Thursday, July 29, 2021 - link
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Instagram keyboard is amongst the most cherished and the majority of used instagram resources. Each and every customer in the social media foundation uses it in a different way https://apps.apple.com/app/id1503238062">find here Nonetheless, this brilliant computer keyboard will make it much more intriguing and easier for end users. There are many things you can do with this particular typefaces computer keyboard inside the app and so that you can increase its power, this is a list of handful of suggestions.
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Consumption of instagram fonts within each iphone app and in all programs including Twitter and facebook is greatly increasing. Many people like to use this particular computer keyboard to enable them to make their information far more interesting. The reason why the majority of people like instagram is its vibrant and different look. Every person feels like publishing anything exclusive on instagram. To make your profile a lot more exclusive, you can consider to utilize several of the special fonts within every mobile app.
It is possible to alter your computer keyboard fonts manually by downloading them online or you can even buy them manually mounted on your computer by browsing various websites supplying typeface typefaces without charge. There are numerous of websites offered that offer cost-free fonts for usage in every programs which include instagram. This way, you are able to make positive changes to key pad typefaces anytime and anywhere you need. These fonts are extremely simple to put in on your computer system and also it is possible to download it directly from a certain site.
Installing typefaces on your pc is not difficult. Just click on the typeface typefaces and also the proper site will unlock. There you can opt for the kind and scale of the font which you prefer to use in the apps. The majority of the font keyboards permits the person to make use of only one kind of font in the apps along with the customer also can modify them as many times he/she wants.
Key-board is a great device that permits you to make unique and eye-catching pictures, text messages and images. Should you be an instagram user, you need to have observed the many graphics uploaded by various end users. Everybody utilizes instagram for different uses. Nonetheless, none is aware the importance of instagram typefaces. So, if you wish to have more consideration and make amazing images with instagram, change your keyboard font in the instagram app and save your time and money.