What about ECC memory for automotive devices even for registers as well as ram in these devices (perhaps elsewhere as well) to help against memory induced errors?
I wonder what level of functional safety they're taking credit for due to this "compared results" in the same processor approach.
typically SIL or ASIL components using redundancy for reduction of probability of dangerous failure would use two (or more) separate processors entirely, not just two threads in the same processor. not entirely sure where they think the risk reduction occurs honestly...
Likely. SMT is used to eliminate pipeline bubbles and thus improve the IPC of a pipeline. If CA65 is meant to be a throughput core, then SMT makes sense, as you've guessed it, to better utilize the width of the pipeline. A related reason would be to address codes dominated by high-latency, pipelined ALU ops -- again, by improving throughput. Also, I disagree with Andrei here: an SMTxN pipeline could be more power-efficient than Nx non-SMT pipelines, depending on the workload. That would mean that the factor by which the single SMT pipeline would be slower than the Nx non-SMT pipelines would be less than the factor by which the latter use up more energy than the former.
Sensors, like all input devices, are generally treated as privileged hardware. Applications software does not have direct access to them. ARM has implemented SMT in a way that allows the two threads to be at different "Exception" (privilege) levels.
Without SMT, the 64 bit ARM would have to push a bunch of registers onto the stack, access the sensor and store the value somewhere, then restore the registers. With SMT, one thread (and the registers associated with it) can be be reserved for accessing sensors.
In real time use, sensors are monitored at strictly regular intervals, normally under interrupt. The 32 bit ARM mode has a shadow set of registers for "Fast Interrupt Requests" (FIQ). This is not available in 64 bit mode, but the SMT scheme can emulate - with about 5 times as much register space available.
ARM could have simply extended the FIQ concept to the 64 bit mode, but by adding SMT, they gain a lot of flexibility. As blu42 points out, there are some workloads where SMT can be more power efficient.
I wonder how well protected ARM's SMT implementation is from Spectre-like vulnerabilities? If their SMT is only used in lock-step to check for discrepancies instead of independently presumably this isn't a concern.
According to the official A65 TRM: "The Cortex-A65 core implements the PSTATE SSBS (Speculative Store Bypass Safe) bit that supports software mitigation for Spectre Variant 4 introduced in the Armv8.5-A extension." (https://developer.arm.com/documentation/100439/010...
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[email protected] - Tuesday, December 18, 2018 - link
What about ECC memory for automotive devices even for registers as well as ram in these devices (perhaps elsewhere as well) to help against memory induced errors?Wilco1 - Tuesday, December 18, 2018 - link
This is ASIL D, and that requires much more than just DRAM with ECC. See eg. https://www.arm.com/files/pdf/20160628_B02_ATF_Kor...[email protected] - Tuesday, December 18, 2018 - link
Thanks for the write up :)drexnx - Tuesday, December 18, 2018 - link
I wonder what level of functional safety they're taking credit for due to this "compared results" in the same processor approach.typically SIL or ASIL components using redundancy for reduction of probability of dangerous failure would use two (or more) separate processors entirely, not just two threads in the same processor. not entirely sure where they think the risk reduction occurs honestly...
Jorgp2 - Tuesday, December 18, 2018 - link
Did they implement SMT to help fill a wider core?blu42 - Friday, December 21, 2018 - link
Likely. SMT is used to eliminate pipeline bubbles and thus improve the IPC of a pipeline. If CA65 is meant to be a throughput core, then SMT makes sense, as you've guessed it, to better utilize the width of the pipeline. A related reason would be to address codes dominated by high-latency, pipelined ALU ops -- again, by improving throughput. Also, I disagree with Andrei here: an SMTxN pipeline could be more power-efficient than Nx non-SMT pipelines, depending on the workload. That would mean that the factor by which the single SMT pipeline would be slower than the Nx non-SMT pipelines would be less than the factor by which the latter use up more energy than the former.ScouserLes - Saturday, December 29, 2018 - link
Sensors, like all input devices, are generally treated as privileged hardware. Applications software does not have direct access to them. ARM has implemented SMT in a way that allows the two threads to be at different "Exception" (privilege) levels.Without SMT, the 64 bit ARM would have to push a bunch of registers onto the stack, access the sensor and store the value somewhere, then restore the registers. With SMT, one thread (and the registers associated with it) can be be reserved for accessing sensors.
In real time use, sensors are monitored at strictly regular intervals, normally under interrupt. The 32 bit ARM mode has a shadow set of registers for "Fast Interrupt Requests" (FIQ). This is not available in 64 bit mode, but the SMT scheme can emulate - with about 5 times as much register space available.
ARM could have simply extended the FIQ concept to the 64 bit mode, but by adding SMT, they gain a lot of flexibility. As blu42 points out, there are some workloads where SMT can be more power efficient.
ltcommanderdata - Wednesday, December 19, 2018 - link
I wonder how well protected ARM's SMT implementation is from Spectre-like vulnerabilities? If their SMT is only used in lock-step to check for discrepancies instead of independently presumably this isn't a concern.shervinemami - Tuesday, March 8, 2022 - link
According to the official A65 TRM: "The Cortex-A65 core implements the PSTATE SSBS (Speculative Store Bypass Safe) bit that supports software mitigation for Spectre Variant 4 introduced in the Armv8.5-A extension."(https://developer.arm.com/documentation/100439/010...