^ they should lol, this way here no one can truly complain as it will always fall in the ∞ numbering, I think the next best look for a simple numeral is omega Ω which of course would signify "the end" course in their case it just means a stopping ground to unload all them dead numbered bodies LOL
Essentially zero. It takes way too much time to rework an architecture for a smaller process node than AMD would have had, even if they were the very first to be informed of this new node.
Using same design rules actually means you don't have to touch previously lay down design, you just re root it because N6 is the same N7 with used different denser lib.
It is NOT a smaller nod. And since design rules are the same, it's very possible Zen2+, likely used on APUs in late 2020 or later, are using a variant of this.
If Zen2 is N7 (and not, say, N7+), then Zen2+ is certain to be N6. No redesign, just pay for masks and do the post-silicon characterization. Meanwhile, the design team is working on Zen3 in N5. It's a no-brainer. Looks a lot like Zen to Zen+ from 14nm to 12nm.
Zen 2+ has never been mentioned. Zen 3 will come after Zen 2.
That said, I can see where AMD might want to use this, for example for GPUs or APUs after Renoir. For a mainstream APU it seems reasonable to use a mainstream process that nevertheless is denser than 7nm. A long term entry level 4C/8T APU could be a nice N6 option.
If TSMC is telling the truth that N6 is essentially a drop in "fit" for an N7 design, then, AMD MIGHT, and I do mean MIGHT bother to switch the 4000 series APUs to N6 to increase wafer yield. It is suspected that the next batch of APUs from AMD will aim for higher performance than the current ones, and will require more cores and more cache, on top of having a substantial iGPU section. That's going to be a largish design that will absolutely benefit from having maximum circuit density to be able to also fit into the existing package sizes they are using in the mobile space to keep integrator costs low.
If it really is that much denser, that would allow AMD to make an APU that has 8 cores, 16MB of L3, and a 12 or so CU implementation of NAVI or VEGA+ and still come in smaller than the 2700u that's currently on the market.
No, Zen2 actually has many architectural improvements, Zen+ has close to ZERO uArch improvement. 2020 will be the same "Zen+"-style process optimization year. And a later roadmap didn't list Renoir and Vermeer as Zen3
likely AMD will be going the 7nm+ or I suppose this for the 2020 refresh Zen2+ (the 7nm+ from their regular 7nm is already a touch better, at least AMD (as well as others) will have a nice selection for different product segments
Sounds a lot like TSMC is looking for guinea pigs for their first full extreme UV-based manufacturing fab. The interesting thing here is that TSMC hasn't named a single client who is making the "easy" move to the 6 nm process. It looks like most customers will go with the 7 nm FF+ process for their newer chips, as that node seems to have tangible upsides vs. their current 7 nm process, while that's up in the air for the 6 nm process.
Apple will probably be the only costumer for N7+, HiSilicon (Huawei) is currently making it's Kirin 985 on N7 EUV, Qualcomm could be first to utilise N6. Each & every current user of N7 (expects Apple) will probably go for N6 as it doesn't cost them much to switch to it while they save 20% on price per unit made.
N7+ =N7 EUV which Huawei will use. Apple will use a custom/semicustom N7 (no EUV) also I bet that next years top Snapdragon will be made by Samsung (they only skipped this year because Samsung didn't have 7nm ready and they did this only for the flagship SoC, all the rest are still fabbed by Samsung).
TSMC themselves said only few customers were interested in 7+, expecting only 30 million usd in revenue. What's a little surprising is introduction of N6, after already promoting 5nm or N5, and expecting most to choose 6. It suggests that N5 is less compelling than previously thought.
It would be useful to have either a standalone article, or some boiler-plate for articles such as this, which delineates how much new tooling from the likes of ASML is required to make the transition to a 'smaller' node. In this case, is TSMC leveraging proprietary process changes on existing tooling (that all vendors have), or are they beneficiaries of new tooling from the likes of ASML.
One way or the other, is their a coming step where all vendors are dependent on ASML/et. al. devising (at least some) new machines?
Given ASML is the only player in EUV and all future nodes now depend on EUV, they are 100% dependent on machines from ASML and also the future High NA EUV machines from ASML
Some kind of talent loss earlier in the decade, or advancement of management from a certain country which has zero successful high-tech companies, or both.
How well would you do in a Formula-1 race? The cars are fairly similar but who drives it matters. The same is true for processes, the machines are the same, but you need to design a complex recipe to build working chips.
TSMC has done so well by taking small steps at a time to reduce the risk when moving to a new technology - for example they based their first FinFET process on the already mature 20nm process. Intel tried "hyperscaling", making several complex changes in one go, which is very risky and didn't work out. As a result TSMC has already started producing chips at twice the density of Intel's 10nm process.
"The same is true for processes, the machines are the same, but you need to design a complex recipe to build working chips."
given. but the question isn't about process, alone. the question is what, specifically, allows one vendor, TSMC, to produce 'smaller' node than other vendors using the same 'commodity' machinery? does it just boil down to more complex masking? or some other specific steps? and so on. I assume that how these machines work is well known to those in the business, i.e. they ain't many secrets. granted, Xnm stopped meaning the same set of dimensions of the same features years ago.
In principle you can get the same maximum density when using the same machines. TSMC 7nm and initial Intel 10nm get around 100 million transistors/mm^2. However while Intel reduced their 10nm density to get it working, TSMC has already moved to the next generation machines using EUV which support 175 mT/mm^2.
However it's worth understanding there is a huge amount of design just to get a working transistor. It takes around 75 masks and hundreds of steps during 3-4 months using exotic metals and corrosive chemicals to create transistors and wire them up. Any minor issue can destroy many millions worth of chips. That includes chemicals which aren't pure enough as TSMC found out.
bet too much on novel new metals (Ruthenium and Cobalt) to reduce parasitic capacitance, and quad patterning in lieu of EUV and it sounds like neither bet paid off.
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Sychonut - Wednesday, May 1, 2019 - link
Looking forward to Intel's 14+++++++.valinor89 - Wednesday, May 1, 2019 - link
Let's call it 14∞ and be done with it.RSAUser - Thursday, May 2, 2019 - link
I can't easily hit infinity on my keyboard, so that's a negative.Dragonstongue - Thursday, May 2, 2019 - link
^ they should lol, this way here no one can truly complain as it will always fall in the ∞ numbering, I think the next best look for a simple numeral is omega Ω which of course would signify "the end" course in their case it just means a stopping ground to unload all them dead numbered bodies LOLlevizx - Friday, May 3, 2019 - link
Then there is 14∞+bug77 - Thursday, May 2, 2019 - link
14# ;)Ironchef3500 - Thursday, May 2, 2019 - link
Aren't we all!serendip - Wednesday, May 1, 2019 - link
They're exploiting the mass effect already.PeachNCream - Thursday, May 2, 2019 - link
You mean they're telling us there won't be an A, B, or C ending but they're giving us an A, B, or C ending?AshlayW - Wednesday, May 1, 2019 - link
How likely is it that AMD's Zen2+ will be on this process instead of N7+?jordanclock - Wednesday, May 1, 2019 - link
Essentially zero. It takes way too much time to rework an architecture for a smaller process node than AMD would have had, even if they were the very first to be informed of this new node.coburn_c - Wednesday, May 1, 2019 - link
u wot m8ZolaIII - Thursday, May 2, 2019 - link
Using same design rules actually means you don't have to touch previously lay down design, you just re root it because N6 is the same N7 with used different denser lib.levizx - Friday, May 3, 2019 - link
It is NOT a smaller nod. And since design rules are the same, it's very possible Zen2+, likely used on APUs in late 2020 or later, are using a variant of this.AMD is not using vanilla N7FF in the first place.
Colorado_Chips - Wednesday, May 1, 2019 - link
If Zen2 is N7 (and not, say, N7+), then Zen2+ is certain to be N6. No redesign, just pay for masks and do the post-silicon characterization. Meanwhile, the design team is working on Zen3 in N5. It's a no-brainer. Looks a lot like Zen to Zen+ from 14nm to 12nm.Colorado_Chips - Wednesday, May 1, 2019 - link
Okay, just saw a slide showing Zen3 in 7nm+, soooo ... never mind.Eris_Floralia - Wednesday, May 1, 2019 - link
No. Zen2 isn't on N7+. And N6 is 2020Q1 risk production. There's nothing called Zen2+.levizx - Wednesday, May 8, 2019 - link
Then what do you think Ryzen 4000 APU, which certainly wouldn't be out before late 2020, would be called?ET - Thursday, May 2, 2019 - link
Zen 2+ has never been mentioned. Zen 3 will come after Zen 2.That said, I can see where AMD might want to use this, for example for GPUs or APUs after Renoir. For a mainstream APU it seems reasonable to use a mainstream process that nevertheless is denser than 7nm. A long term entry level 4C/8T APU could be a nice N6 option.
lightningz71 - Thursday, May 2, 2019 - link
If TSMC is telling the truth that N6 is essentially a drop in "fit" for an N7 design, then, AMD MIGHT, and I do mean MIGHT bother to switch the 4000 series APUs to N6 to increase wafer yield. It is suspected that the next batch of APUs from AMD will aim for higher performance than the current ones, and will require more cores and more cache, on top of having a substantial iGPU section. That's going to be a largish design that will absolutely benefit from having maximum circuit density to be able to also fit into the existing package sizes they are using in the mobile space to keep integrator costs low.If it really is that much denser, that would allow AMD to make an APU that has 8 cores, 16MB of L3, and a 12 or so CU implementation of NAVI or VEGA+ and still come in smaller than the 2700u that's currently on the market.
HStewart - Thursday, May 2, 2019 - link
Would be simple call Zen 2 Zen++ and Zen 3 Zen+++levizx - Wednesday, May 8, 2019 - link
No, Zen2 actually has many architectural improvements, Zen+ has close to ZERO uArch improvement. 2020 will be the same "Zen+"-style process optimization year. And a later roadmap didn't list Renoir and Vermeer as Zen3Santoval - Thursday, May 2, 2019 - link
There is not going to be a Zen2+, after Zen 2 comes Zen 3.peevee - Thursday, May 2, 2019 - link
Are you an executive at AMD?AshlayW - Thursday, May 2, 2019 - link
Ah right. I just assumed they would make a Zen2+.Dragonstongue - Thursday, May 2, 2019 - link
likely AMD will be going the 7nm+ or I suppose this for the 2020 refresh Zen2+ (the 7nm+ from their regular 7nm is already a touch better, at least AMD (as well as others) will have a nice selection for different product segmentseastcoast_pete - Wednesday, May 1, 2019 - link
Sounds a lot like TSMC is looking for guinea pigs for their first full extreme UV-based manufacturing fab. The interesting thing here is that TSMC hasn't named a single client who is making the "easy" move to the 6 nm process. It looks like most customers will go with the 7 nm FF+ process for their newer chips, as that node seems to have tangible upsides vs. their current 7 nm process, while that's up in the air for the 6 nm process.ZolaIII - Thursday, May 2, 2019 - link
Apple will probably be the only costumer for N7+, HiSilicon (Huawei) is currently making it's Kirin 985 on N7 EUV, Qualcomm could be first to utilise N6. Each & every current user of N7 (expects Apple) will probably go for N6 as it doesn't cost them much to switch to it while they save 20% on price per unit made.porcupineLTD - Thursday, May 2, 2019 - link
N7+ =N7 EUV which Huawei will use. Apple will use a custom/semicustom N7 (no EUV) also I bet that next years top Snapdragon will be made by Samsung (they only skipped this year because Samsung didn't have 7nm ready and they did this only for the flagship SoC, all the rest are still fabbed by Samsung).dudedud - Thursday, May 2, 2019 - link
Any source on "N7 PRO" being non EUV?Its hard to believe that Apple will not choose an advanced EUV process.
Anymoore - Thursday, October 3, 2019 - link
TSMC themselves said only few customers were interested in 7+, expecting only 30 million usd in revenue. What's a little surprising is introduction of N6, after already promoting 5nm or N5, and expecting most to choose 6. It suggests that N5 is less compelling than previously thought.FunBunny2 - Thursday, May 2, 2019 - link
It would be useful to have either a standalone article, or some boiler-plate for articles such as this, which delineates how much new tooling from the likes of ASML is required to make the transition to a 'smaller' node. In this case, is TSMC leveraging proprietary process changes on existing tooling (that all vendors have), or are they beneficiaries of new tooling from the likes of ASML.One way or the other, is their a coming step where all vendors are dependent on ASML/et. al. devising (at least some) new machines?
Speedfriend - Thursday, May 2, 2019 - link
Given ASML is the only player in EUV and all future nodes now depend on EUV, they are 100% dependent on machines from ASML and also the future High NA EUV machines from ASMLMeteor2 - Thursday, May 2, 2019 - link
Which always leaves me wondering how come Intel has made such a mess of their process shrink, while TSMC have smashed it.peevee - Thursday, May 2, 2019 - link
Some kind of talent loss earlier in the decade, or advancement of management from a certain country which has zero successful high-tech companies, or both.Wilco1 - Thursday, May 2, 2019 - link
How well would you do in a Formula-1 race? The cars are fairly similar but who drives it matters. The same is true for processes, the machines are the same, but you need to design a complex recipe to build working chips.TSMC has done so well by taking small steps at a time to reduce the risk when moving to a new technology - for example they based their first FinFET process on the already mature 20nm process. Intel tried "hyperscaling", making several complex changes in one go, which is very risky and didn't work out. As a result TSMC has already started producing chips at twice the density of Intel's 10nm process.
FunBunny2 - Friday, May 3, 2019 - link
"The same is true for processes, the machines are the same, but you need to design a complex recipe to build working chips."given. but the question isn't about process, alone. the question is what, specifically, allows one vendor, TSMC, to produce 'smaller' node than other vendors using the same 'commodity' machinery? does it just boil down to more complex masking? or some other specific steps? and so on. I assume that how these machines work is well known to those in the business, i.e. they ain't many secrets. granted, Xnm stopped meaning the same set of dimensions of the same features years ago.
Wilco1 - Saturday, May 4, 2019 - link
In principle you can get the same maximum density when using the same machines. TSMC 7nm and initial Intel 10nm get around 100 million transistors/mm^2. However while Intel reduced their 10nm density to get it working, TSMC has already moved to the next generation machines using EUV which support 175 mT/mm^2.However it's worth understanding there is a huge amount of design just to get a working transistor. It takes around 75 masks and hundreds of steps during 3-4 months using exotic metals and corrosive chemicals to create transistors and wire them up. Any minor issue can destroy many millions worth of chips. That includes chemicals which aren't pure enough as TSMC found out.
drexnx - Thursday, May 2, 2019 - link
bet too much on novel new metals (Ruthenium and Cobalt) to reduce parasitic capacitance, and quad patterning in lieu of EUV and it sounds like neither bet paid off.